Defective block handling in a flash memory device

Details Defective block handling in a flash memory device Defective block handling in a flash memory device

2008-09-09

2008-09-09

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S185090, C365S185110, C365S185290

Reexamination Certificate

active

11789725

ABSTRACT:
A method and circuit that remaps, to a single redundant memory block, defective rows from amongst a plurality of defective memory blocks. The circuit determines which rows of each memory block is defective and maps any further access to those rows to the redundant memory block. During an erase operation of the remapped memory rows, the selected rows are biased with an erase voltage, the source line and tub are biased at some high voltage that can be greater than VCC. The unselected word lines are biased at a voltage that is substantially equal to the substrate voltage.

REFERENCES:
patent: 5293593 (1994-03-01), Hodge et al.
patent: 5630097 (1997-05-01), Orbits et al.
patent: 5699306 (1997-12-01), Lee et al.
patent: 5867642 (1999-02-01), Vivio et al.
patent: 5987632 (1999-11-01), Irrinki et al.
patent: 6262926 (2001-07-01), Nakai
patent: 6477612 (2002-11-01), Wang
patent: 6496413 (2002-12-01), Taura et al.
patent: 6532181 (2003-03-01), Saito et al.
patent: 7221603 (2007-05-01), Roohparvar

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