Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
1999-11-05
2001-11-20
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S173000, C257S635000, C257S665000, C438S333000, C438S601000
Reexamination Certificate
active
06320243
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and the manufacturing method thereof, and more particularly to a defect removable semiconductor device and the manufacturing method thereof where a fuse can be cut off by laser beam with other adjacent fuses being protected.
2. Description of the Prior Art
As the degree of integration of the dynamic random access memory (DRAM) in the semiconductor device gets higher, the size of the memory cell of the DRAM gets smaller. If one of many DRAM memory cells has a defect, the DRAM is not properly functioning to be determined as a defective product However, it may be possible to have a small number of defective memory cells while the degree of integration of the DRAM is kept high in the semiconductor element. If all those DRAMs are discarded as defective products, the yield of final products is greatly lowered. It has been regarded as unproductive.
Recently, redundancy cells have additionally been installed in the DRAM along with the main memory cells. In case that a defect occurs in one of the main memory cells, a redundancy cell replaces the defective main memory cell to improve the yield of the DRAMs.
The DRAM redundancy memory cells are installed in respective sub-array blocks. A spare row/column line has been previously disposed at every 256K cell array. The defective main memory cell is replaced by the spare redundancy memory cell in an unit of the row/column line. When wafer levels of operations are completed, a defective memory cell is determined and separated at a testing step and then the programming operation which substitutes the address of the defective memory cell with that of a spare memory cell is performed in an internal circuit. Therefore, when the address relating to the defective row/column line is inputted, the spare row/column line is selected for the defective row/column line.
The programming operation includes melting down a fuse with over-current, burning down a fuse with laser beam, shorting a junction with a laser beam and programming into an erasable and programmable ROM (EPROM) memory cell, etc. Among them, cutting off the fuse with laser beam is commonly used because of operational simplicity and effectiveness and easiness in layout of fuses. Polycrystalline silicon wiring or metal wiring is used for fuses. In relation to this, a thesis titled
Laser Programmable Redundancy And Yield Improvement In A
64
K Dynamic Random
-
Access Memory
has been disclosed in IEEE Transactions on Electron Devices, Vol. ED-26, pp. 853-860, 1979.
On the other hand, there are physical and logical programming methods for replacing a defective column/row line with a spare one by means of the laser beam. The physical programmable method includes replacing a defective column/row line with a spare one and deactivating a decoder related to the defective column/row line.
In the former method, there is no loss of operational speed caused by a repairing process with the redundancy cells because one defective column/row line is directly replaced by one spare column/row line and no time is needed for comparing addresses to deactivate the defective column/row line. However, this method is known to be disadvantageous in keeping a high degree of integration due to the size and accuracy of fuse blow, since the layout pitches of the fuse and the word line should be matched.
Therefore, in the latter method, which has been mainly used, the fuse is inserted into a decoder circuit where a decoder related to the defective column/row line is deactivated. Generally, the DRAM shares a decoder in every 4 word lines, widening the layout pitch of the fuse. However, this method has been proved unsuitable in maintaining the high degree of integration because the number of fuses increases for the higher degree of integration.
In the aforementioned logic programmable method, when the address related to the defective word line is inputted, a pulse is generated to disable a normal decoder, thereby controlling to block the operation of normal word lines and to operate only the spare word lines. In this method, a signal, generated as a result of the determination at the address comparison circuit where it is determined whether the inputted address selects a defective cell, non-selects normal decoders, so that the same amount of time as being taken for determination in the comparison circuit is lost for accessing.
Besides, there are other methods for improving repairing efficiency by installing a plurality of spare word lines to replace more defective cells with a predetermined number of spare cells and for maintaining the high efficiency in repairing a smaller number of fuses.
On the other hand, a great attention has recently been drawn to a merged DRAM/logic (MDL) process, which is characterized by superior function of transistors, a high degree of integration in memory, an advantage of multi-layered wiring process and the composition of one chip including logic circuit and DRAM. Because the multi-layered wiring is not required in the conventional DRAM process, a polycrystalline silicon layer has been used as a fuse. However, instead of the polycrystalline silicon used as a word line in the conventional method, a part of the uppermost metal wire is used as a fuse in the MDL process requiring the multi-layered wiring, because the surface difference of the upper layer insulator film is large.
In the conventional semiconductor element with the MDL process, as shown in
FIG. 1
, insulating interlayer
20
is deposited at a main memory cell region and a redundancy memory cell region of the substrate
10
. Final metal wires
30
are arranged on the insulating interlayer
20
. A first protective layer
40
covers the insulating interlayer
20
which includes the metal wire
30
.
The metal wire
30
is composed of a multi-layered structure having a Ti/TiN layer for a fuse
31
at the bottom, an aluminum layer
33
at the middle and TiN
35
layer for a cap at the top. However, there are a mono-layered structure of Ti/TiN layers
31
a
,
31
b
,
31
c
,
31
d
in an aperture portion of the first protective layer
40
.
For a brief description, all the units installed in the conventional method below the substrate
10
, such as transistors, accumulative capacitors, insulating interlayer, contact plugs, word lines, bit line, metal wire, etc., are not shown in the drawings.
In the semiconductor element thus constructed, if the fuse of the metal wire needing defect removal is Ti/TiN
31
a
, it is cut off by a laser beam (not shown) of 0.15 &mgr;J.
REFERENCES:
patent: 5585662 (1996-12-01), Ogawa
patent: 5650355 (1997-07-01), Fukuhara et al.
patent: 5851903 (1998-12-01), Stamper
patent: 5936296 (1999-08-01), Park et al.
patent: 5976917 (1999-11-01), Manning
patent: 0241046-A2 (1987-10-01), None
Cenker et al., A Fault-Tolerant 64K Dynamic Random-Access Memory, IEEE Transactions on Electron Devices, vol. ED-26, No. 6, Jun. 1979, pp. 853-860.
Jeong Hee-Geun
Kim Yong-Shik
Lee Eddie
Myers Bigel & Sibley & Sajovec
Samsung Electronics Co,. Ltd.
Warren Matthew E.
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