Defect reference system automatic pattern classification

Details Defect reference system automatic pattern classification Defect reference system automatic pattern classification

2000-05-31

2002-10-15

Hoff, Marc S (Department: 2857)

Data processing: measuring, calibrating, or testing

Measurement system

Statistical measurement

C702S084000, C702S117000, C702S118000

Reexamination Certificate

active

06466895

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method and apparatus for identifying the causes of inspected defects in a manufactured article. The invention has particular applicability for in-line inspection of semiconductor wafers during manufacture of high-density semiconductor devices with submicron design features.
BACKGROUND ART
Current demands for high density and performance associated with ultra large scale integration call for submicron features, increased transistor and circuit speeds and improved reliability. Such demands require formation of device features with high precision and uniformity, which in turn necessitates careful process monitoring, including frequent and detailed inspections of the devices while they are still in the form of semiconductor wafers.
Conventional wafer fabrication process control techniques employ wafer identification schemes, such as bar code labels, for in-process wafer tracking. After the completion of each process step (e.g., oxide growth, etch, clean, sputter, etc.), information related to the wafer lot and the “last visited tool”; i.e., the particular oven, etcher, cleaner, polishing machine, etc. used in processing the lot, is entered into a computer software-implemented database system known as a “manufacturing execution system” (MES). Such information includes wafer identification information, parameters related to the wafers, and process parameters used at the last visited tool. Thus, the MES tracks the completed process steps, the tools at which the process steps were performed, and the wafers on which the process steps were performed.
After the completion of a series of process steps, and/or after the completion of a critical process step, such as formation of a complex photoresist mask, a number of wafers in a lot are inspected, typically at a stand-alone inspection tool, per instructions from the MES. At the inspection tool, the surface of the wafer to be inspected is typically scanned by a high-speed inspection device; for example, an opto-electric converter such as a CCD (charge-coupled device), a scanning electron microscope (SEM) or a laser. Typically, the inspection tool informs the MES when it has completed its inspection. Statistical methods are thereafter employed by the inspection tool to produce a defect map showing suspected locations on the wafer having a high probability of a defect. If the number and/or density of the potential defects reach a predetermined level, an alarm is sounded, indicating that a more detailed look at the potential defect sites is warranted.
A review of the potential defect sites is then conducted using the defect map, either at the inspection tool or at a separate stand-alone review station, typically by comparing images of suspected defect sites with reference images to positively determine the presence of a defect, and then analyzing the images to determine the nature of the defect (e.g., a defective pattern, a particle, or a scratch). Common wafer inspection techniques used by wafer fabricators include light scattering techniques, optical techniques, SEM's and energy dispersive spectroscopy (EDS). Other well-known wafer inspection methods are also commonly employed, including atomic force microscopy (AFM), raman, ultrapoint, transmission electron microscopy (TEM), metapulse, photoluminescence and electron spectroscopy for chemical analysis (ESCA). Each of the foregoing methods furnishes different information relating to the defect; for example, AFM can reveal its size and shape, while EDS and ESCA can reveal its chemical composition.
In current “state of the art” wafer processing facilities, process data from the MES, and inspection and review results from the inspection tools and review stations are periodically downloaded to another stand-alone computer software-implemented system called a “yield management system” (YMS), which employs statistical process control methods to monitor process quality. If the YMS determines that the process is performing outside predetermined control limits, it generates data, such as a list of tools visited by wafers exhibiting defects and the process parameters used at those tools, which are helpful in diagnosing processing problems. The user may then analyze this data in an attempt to isolate the causes of the defects.
Disadvantageously, defects are not described in a standard way across the industry (i.e., defect descriptions differ between fabrication facilities within one device fabrication company, from one device fabricator to another, and between fabricators and equipment suppliers), thereby hindering attempts at defect identification and causal diagnoses. For example, one class of defects are called “fried egg” defects in Japan, but are called “space ship” defects by some fabricators in the United States. Thus, translation and exchange of information between fabricators and equipment suppliers of different cultures is made more difficult.
Moreover, even when defects are identified, they cannot be quickly or easily linked to a root cause. For example, although the YMS can identify the tools and process parameters of a process performing outside its control limits, the YMS cannot identify the most likely tool or process parameter at fault when a particular defect is detected. Still further, even if a particular tool is identified as the source of a defect, the YMS cannot link the defect with a particular fault in the tool, a material failure (i.e., a part failure) or a particular process condition.
There exists a need for a methodology for in-process inspection of semiconductor wafers that identifies defects in a standardized way. There further exists a need for an inspection methodology that relates the tools visited by the wafers and reliability information of those tools to detected defects in order to readily identify the root causes of defects, thereby enabling early corrective action to be taken. This need is becoming more critical as the density of surface features, die sizes, and number of layers in devices increase, requiring the number of defects to be drastically reduced to attain an acceptable manufacturing yield.
SUMMARY OF THE INVENTION
An advantage of the present invention is the ability to identify defects in a manufactured article, such as a semiconductor wafer, in a standardized qualitative manner, thereby allowing information relating to the defect to be easily linked to the defect, stored and searched. A further advantage of the present invention is the ability to include, in the identification of a defect, information relating to its cause, thereby enabling efficient identification of process problem areas, and the relation of defect causes to corrective action.
According to the present invention, the foregoing and other advantages are achieved in part by a method of classifying a feature of an article, which method comprises determining attributes of the feature; generalizing the attributes by associating each attribute with one or more categories, each category being a subset of one of a plurality of database objects associated with the attributes; assigning each category a symbol; arranging the symbols of the categories in a predetermined sequence to form an identifier for the feature; and storing the identifier in a database.
Another aspect of the present invention is a computer-readable medium bearing instructions for executing the above steps of the present methodology.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings-and description are to be regarded as illustrative in nature,

Affiliated with

Also associated with

Rating

Defect reference system automatic pattern classification does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Defect reference system automatic pattern classification, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Defect reference system automatic pattern classification will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2999416