Defect-minimizing, topology-independent planarization of...

Details Defect-minimizing, topology-independent planarization of... Defect-minimizing, topology-independent planarization of...

2005-05-17

2005-05-17

Wilson, Christian (Department: 2824)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S493000, C438S496000, C438S694000

Reexamination Certificate

active

06893968

ABSTRACT:
A process for planarizing a process layer having structures and has been applied to a working surface of a semiconductor device, includes abrading the process layer down to the working surface using a polishing device. The working surface is planarized, and a defect density in the working surface is minimized and the polishing process is topology-independent.

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Schiltz et al., Plasma etch-back planarization coupled to chemical mechanical polishing for sub 0.18 μm shallow trench isolatio technology,J. Vac. Sci. Technol. A, 18 (Jul./Aug. 2000) 1313.

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