Defect management for interface to electrically-erasable...

Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability

Reexamination Certificate

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Details

C711S152000

Reexamination Certificate

active

06405323

ABSTRACT:

TECHNICAL FIELD
The present invention relates to defect management in flash memory devices and, in particular, to an interface controller to such a memory that includes circuitry to reliably track, and prohibit access to, defective sectors.
BACKGROUND
The use of electrically erasable memory is well-known in the art. For example, standards for “flash” memory and circuits for controlling access to the flash memory have been defined by the Personal Computer Memory Card International Association (PCMCIA) and Compact Flash Association (CFA). PCMCIA-compliant cards have been used with portable computers as an adjunct to (or instead of) a hard drive and, more recently, for such devices as digital cameras.
Portions of a flash memory may be defective—for example, due to defects of manufacture or because they have simply worn out from use. It is important to track which portions of the flash memory are defective so that there is no attempt by other circuitry (such as a microprocessor) to access these defective portions. However, it is a challenge to reliably track such defects, and to efficiently determine whether a particular portion of a memory is defective.
SUMMARY
A circuit interfaces a host processor to an electrically-erasable memory in a memory space, such as a flash media. The memory space defines a plurality of segments, and each of the segments includes a plurality of sectors.
A media interface circuit regulates access by the host processor to the electrically-erasable memory in the memory space. Sector valid indication reading circuitry reads at least one sector valid indication from a segment of the media. Sector valid determination circuitry determines a non-defective sector from the at least one sector valid indication read.
Sector level segment defect map indication reading circuitry reads a sector-level segment defect map from the sector determined to be non-defective. Sector defect determination circuitry determines, from the sector-level segment defect map read, sectors within the segment that are valid.
Access regulation circuitry regulates access to the memory space at least in part on the determinations by the sector defect determination circuitry.


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