Semiconductor device manufacturing: process – Gettering of substrate – By layers which are coated – contacted – or diffused
Reexamination Certificate
1999-06-17
2001-08-14
Meier, Stephen D. (Department: 2822)
Semiconductor device manufacturing: process
Gettering of substrate
By layers which are coated, contacted, or diffused
C438S402000, C438S471000
Reexamination Certificate
active
06274460
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to forming a gettering zone in a semiconductor substrate and, more particularly, to both manufacturing methods and substrate structures for improving device performance by gettering defects in the substrate.
BACKGROUND OF THE INVENTION
Traditionally, trenches in a semiconductor substrate are oxidized and refilled with polysilicon material or entirely filled with deposited oxide. The trench refill process completely fills the trenches and leaves no voids. Voids on the surface of the polysilicon, when oxidized, cause stress within the substrate which subsequently generate yield reducing defects. Manufacturers of semiconductor substrates, therefore, strive to great lengths to avoid stress within the substrate. For example in U.S. Pat. No. 5,448,102 (Gaul et al.), Gaul et al. disclose a process to avoid and reduce stress in a semiconductor substrate that is induced by filling trenches.
Manufacturers also strive to remove or getter impurities. Often heavy elements, such as iron, contaminate device wafers. Those impurities can be attracted to gettering sites that are spaced from the front surface of the wafer where devices arc formed. Typical gettering mechanisms include abrading the back surface of the wafer or coating the back surface with a gettering agent, such as polysilicon. Oxygen can be a gettering agent. Thermal processing is used to form zones in the front surface that are denuded of oxygen. Impurities are captured in the remaining oxygen sites that are in the wafer but below the front surface and beneath the denuded zones.
SUMMARY OF THE INVENTION
Contrary to conventional wisdom, we found that some stress in predetermined regions of a semiconductor substrate is beneficial. Such stress creates a getteling zone. The gettering zone attracts impurities in the substrate and is beneficial to the substrate. The gettering zone is located on the front surface of the wafer, preferably in a sacrificial region outside the region holding the integrated circuit.
In contrast to the conventional process to reduce stress, the present invention induces stress and simultaneously form a zone for gettering impurities in an integrated circuit structure. The structure comprises a monocrystalline semiconductor device substrate. The substrate comprises an upper portion suitable for device formation. The upper portion is divided into an active region and an inactive region. There is an integrated circuit or at least one active device on the active region and at least one gettering trench on the inactive area. The gettering trench comprises a dielectric layer on the sidewalls and the floor of the trench and the remainder of the trench comprises a filling material. At least one void is fabricated within the filling material. The material defining the void is polysilicon. When it is oxidized, pressure is applied to the substrate. That pressure induces stress in the adjacent inactive region and generates defects in the crystal lattice structure of the monocrystalline semiconductor. The defects create a gettering zone that surrounds the trench and attracts impurities.
The gettering site is in the front surface of the device wafer. The location is especially useful in bonded and silicon-on-insulator wafers. Those wafers have an oxide layer on the back side of the device wafer. The oxide blocks conventional back side gettering mechanisms. In an alternate embodiment, the gettering site is a trench filled with polysilicon and without voids or oxidation. The polysilicon acts as a gettering agent. The gettering trench is laterally spaced from the integrated circuit to draw the impurities away from it.
In another embodiment the stressed trench and the polysilicon trench are combined. That embodiment provides a gettering site with two gettering mechanisms for drawing impurities away from the integrated circuit: the defects surrounding the gettering trench and the polysilicon inside the trench.
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Delgado Jose A.
McLachlan Craig J.
Brophy Jamie L.
Intersil Corporation
Jaeckle Fleischmann & Mugel LLP
Meier Stephen D.
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