Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Reexamination Certificate
2003-06-06
2004-08-31
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
C438S046000, C438S047000, C438S077000, C438S312000, C438S602000, C438S603000, C438S604000, C438S022000, C438S702000, C438S606000, C438S902000, C438S962000, C257S012000, C257S014000, C257S021000, C257S085000, C257S094000, C257S190000
Reexamination Certificate
active
06784074
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention pertains to the field of semiconductor devices. More particularly, the invention pertains to fabricating defect-free epitaxial layers for semiconductor device applications.
2. Description of the Related Art
Propagating defects, including threading dislocations, screw dislocations, stacking faults, and antiphase boundaries, play a negative role in semiconductor devices, often limiting or even ruining their performance. Propagating defects can act as strong scattering centers for carriers, thus reducing their mobility and limiting the performance of many semiconductor devices. Some of these devices include heterojunction bipolar transistors (HBT), field effect transistors (FET), and high electron mobility transistors (HEMT). Propagating defects can also act as centers of non-radiative recombination, thus ruining performance of light-emitting devices like light emitting diodes (LED), optical amplifiers, and semiconductor diode lasers. During device operation, particularly at elevated temperatures or at high power of light, defects can propagate through the device structure and multiply themselves, thus reducing the operating lifetime of the device.
Some reasons for the extended defects in a semiconductor heterostructure include, but are not limited to:
lattice mismatch between an epilayer and a substrate (for example in the case of an epilayer having a thickness exceeding the critical thickness against plastic relaxation);
precipitates of point defects and impurities (in the substrates);
statistical irregularities during crystal growth (in both the substrate and the epilayer);
dirt on the substrate surface (generating defects in the epilayer);
nucleation of surface defects (for example “oval defects” in molecular beam epitaxy) due to local surface oxidation or statistical formation of droplets of source materials at the growth surface; and
difference in thermal expansion coefficients between the substrate and the epilayer.
Several approaches have been proposed to reduce the density of dislocations and other defects in epitaxial layers.
Liu et al. proposed the use of Sb as a surfactant during the growth of Si
0.5
Ge
0.5
on Si by molecular beam epitaxy in order to reduce the density of threading dislocations (“
A surfactant
-
mediated relaxed Si
0.5
Ge
0.5
graded layer with a very low threading dislocation density and smooth surface
”, Applied Physics Letters, 75 (11), 1586-1588 (1999)).
Takano et al. used low temperature growth of InGaAs layers on misoriented GaAs substrates by metalorganic vapor phase epitaxy aimed to reduce the density of non-radiative recombination centers and improve the photoluminescence properties of the layers (“
Low temperature growth of InGaAs layers on misoriented GaAs substrates by metalorganic vapor phase epitaxy
”, Applied Physics Letters, 80 (12), 2054-2056 (2002)).
Manfra et al. used a double-stage growth of a GaN buffer layer in the growth of AlN/GaAlN heterostructures on a sapphire substrate by plasma-assisted molecular beam epitaxy, attempting simultaneous optimization of threading dislocation density and surface morphology (“
Dislocation and morphology control during molecular
-
beam epitaxy of AlGaN/GaN heterostructures directly on sapphire substrates”, Applied Physics Letters
81 (8), 1456-1458 (2002)). Nitrogen stabilized conditions were used in the first step, which resulted in a roughened, three-dimensional growth morphology. This morphology appeared to increase dislocation interaction and thus, reduced the number of dislocations, which propagated to the surface. Metal stabilized growth conditions were applied in the second step, which resulted in smoothening of the growth surface.
Contreras et al. used Si delta-doping in the epitaxial growth of GaN on a Si (111) substrate by metalorganic chemical vapor deposition (“
Dislocation annihilation by silicon delta
-
doping in GaN epitaxy on Si
”, Applied Physics Letters 81 (25), 4712-4714 (2002)). This led to bending of screw dislocations and “pairing” with equivalent neighboring dislocations with opposite Burgers vectors. This resulted in the formation of square dislocation loops. However, edge dislocations remained unaffected by silicon delta-doping.
Capewell et al. used the terrace grading profile to produce SiGe virtual substrates. (“
Terrace grading of SiGe for high quality virtual substrates
”, Applied Physics Letters 81 (25), 4775-4777 (2002)).
However, none of these approaches have been very cost-effective or successful in reducing dislocations sufficiently to create a defect-free epitaxial layer.
There is a need in the art for an improved method for selective etching off of defect-rich regions and application of this method to different materials systems and different semiconductor devices.
SUMMARY OF THE INVENTION
A method for fabrication of defect-free epitaxial layers on top of a surface of a first defect-containing solid state material includes the steps of selective deposition of a second material, having a high temperature stability, on defect-free regions of the first solid state material, followed by subsequent evaporation of the regions in the vicinity of the defects, and subsequent overgrowth by a third material, thus forming a defect-free layer.
REFERENCES:
patent: 4806996 (1989-02-01), Luryi
patent: 5019874 (1991-05-01), Inoue et al.
patent: 5075744 (1991-12-01), Tsui
patent: 5091767 (1992-02-01), Bean et al.
patent: 5156995 (1992-10-01), Fitzgerald, Jr. et al.
patent: 5208182 (1993-05-01), Narayan et al.
patent: 5482890 (1996-01-01), Liu et al.
patent: 5719894 (1998-02-01), Jewell et al.
patent: 5859864 (1999-01-01), Jewell
patent: 5888885 (1999-03-01), Xie
patent: 5927995 (1999-07-01), Chen et al.
patent: 5960018 (1999-09-01), Jewell et al.
J.L. Liu, C.D. Moore, G.D. U'Ren, Y.H. Luo, Y. Lu, G. Lin, S.G. Thomas, M.S. Goorsky, K.L. Wang; “A surfactant-mediated relaxed Sio.5Geo.5 graded layer with a very low threading dislocation density and smooth surface”, Appliedd Physics Letters, vol. 75 (11), pp. 1586-1588 (1999).
Y. Takano, K. Kobayashi, H. Iwahori, N. Kuwahara, S. Fuke, S. Shirakata; “Low temperature growth of InGaAs layers on misoriented GaAs substrates by metalorganic vapor phase epitaxy”, Applied Physics Letters, vol. 80 (12), pp. 2054-2056 (2002).
M.J. Manfra, N.G. Weimann, J.W.P. Hsu, L.N. Pfeiffer, K.W. West, S.N.G. Chu; “Dislocation and morphology control during molecular-beam epitaxy of AlGaN/GaN heterostructures directly on sapphire substrates”; Applied Physics Letters 81 (8), pp. 1456-1458 (2002).
O. Conteras, F.A. Ponce, J. Christen, A. Dadgar, A. Krost; “Dislocation annihilation by silicon delta-doping in GaN epitaxy on Si”; Applied Physics Letters 81 (25), pp. 4712-4714 (2002).
A.D. Capewell, T.J. Grasby, T.E. Whall, E.H.C. Parker; “Terrace grading of SiGe for high quality virtual substrates”; Applied Physics Letters 81 (25), pp. 4775-4777 (2002).
“Vertical-Cavity Surface-Emitting Lasers: Design, Fabrication, Characterization, and Applications”; by C.W. Wilmsen, H. Temkin, L.A. Coldren (editors), Cambridge University Press, 1999.
N.N. Ledentsov, V.A. Shchukin; “Novel Concepts for Injection Lasers”, Optical Engineering, vol. 41 (12), pp. 3193-3203 (2002).
N.N. Ledentsov et al., “1.3 um Luminescence and Gain From Defect-Free InGaAs-GaAs Quantum Dots Grown By Metal-Organic Chemical Vapor Deposition.” Semicond. Sci. Technol. 15, 2000, pp. 604-607.
Chen, Y. et al, 1995, “Nucleation of misfit dislocations in In0.2Ga0.8As epilayers grown on GaAs substrates”, Appl. Phys. Lett 66 (4) 499-501.
Huffaker, D.L. et al, 1998, “1.3 &mgr;m room-temperature GaAs-based quantum-dot laser”, Appl Phys. Lett. 73 918), pp 2563-3566.
Blum, O. et al, 2000, “Characteristics of GaAsSb Single-Quantum-Well-Lasers Emitting Near 1.3 &mgr;m”, IEEE Photonics Technology Letters, vol. 12, No. 7, pp 771-773.
Nakahara, K. et al, 1998, “1.3&mgr;m Continuous-Wave Lasing Operation in GaIaNAs Quantum-Well Lasers”, IEEE Photonics Technology Letters, vol 10, No. 4, pp 487-488.
Schlenker, D. et al, 1999, “1.17 &mgr;m Highly
Ledentsov Nikolai
Shchukin Vitaly
Brown & Michaels PC
Fourson George
Maldonado Julio J.
NSC-Nanosemiconductor GmbH
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