Dynamic information storage or retrieval – Condition indicating – monitoring – or testing – Including radiation storage or retrieval
Reexamination Certificate
1999-05-21
2001-07-10
Huber, Paul W. (Department: 2651)
Dynamic information storage or retrieval
Condition indicating, monitoring, or testing
Including radiation storage or retrieval
C369S047140, C369S124150
Reexamination Certificate
active
06259664
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data reproduction in an optical disk system, such as a compact disc player (CDP), or a digital versatile disc (DVD) player, and more particularly, to a defect detection circuit and a method for detecting defects during data reproduction in an optical disk system. The circuit and method prevent erroneous data from being generated that would otherwise arise from a missing or irregularly generated radio frequency (RF) signal due to disc surface scratches or disk defects generated during fabrication.
2. Description of the Related Art
A defect detection circuit in an optical disk data reproduction system according to conventional technology is described as follows with reference to the attached drawings.
FIG. 1
is a schematic block diagram of a conventional defect detection circuit in an optical disk data reproduction system, which includes first and second comparators
11
and
13
, first and second delayers
15
and
17
, and an AND gate
19
.
FIGS. 2A through 2F
are input and output waveforms of the respective elements of the circuit shown in FIG.
1
.
FIG. 2A
shows an RF signal exhibiting a defect.
FIG. 2B
shows the resulting output waveform of the first comparator
11
.
FIG. 2C
shows the resulting output waveform of the second comparator
13
.
FIG. 2D
shows the output waveform of the first delayer
15
, and
FIG. 2E
shows the output waveform of the second delayer
17
.
FIG. 2F
shows the resulting output waveform of the AND gate
19
.
Referring to
FIGS. 1 and 2
, the first comparator
11
receives the RF signal of
FIG. 2A
via a positive input terminal, and compares it to a first compare voltage Vthp received via a negative input terminal. The first comparator
11
generates an output signal at a ‘high’ logic level when the voltage level of the RF signal is higher than that of the first compare voltage Vthp, and generates an output signal at a ‘low’ logic level when the voltage level of the RF signal is lower than that of the first compare voltage Vthp, as shown in FIG.
2
B. The second comparator
13
likewise receives a second compare voltage Vthn via a positive input terminal, and compares it to the RF signal received via a negative input terminal. The second comparator
13
generates an output signal at a ‘high’ logic level when the voltage level of the RF signal is lower than that of the second compare voltage Vthn, and generates an output signal at a ‘low’ logic level when the voltage level of the RF signal is higher than the second compare voltage Vthn.
The first delayer
15
receives the output of the first comparator
11
as an input signal, and when the input signal is at a ‘high’ logic level, the first delayer
15
delays the input signal for a predetermined delay time Td provided by a microprocessor (not shown) to maintain the ‘high’ logic level during the time duration Td, such that the first delayer generates the signal shown in FIG.
2
D. The second delayer
17
receives the output of the second comparator
13
as an input signal, and when the input signal is at a ‘high’ logic level, the second delayer
17
delays the input signal for a predetermined delay time Td, to maintain the ‘high’ logic level during the time duration Td such that the second delayer generates the signal shown in FIG.
2
E.
As a result, the first and second delayers
15
and
17
continuously generate a signal at a ‘high’ logic level when the first and second comparators
11
and
13
generate a signal at a ‘high’ logic level within the delay time Td provided by the microprocessor (not shown), even though the outputs of the first and second comparators
11
and
13
return to a ‘low’ logic level, namely, when the RF signal is normally generated. However, when the ‘high’ logic level is not generated by the first and second comparators
11
and
13
following the delay time Td, namely, when an abnormal RF signal is generated due to defect, the first and second delayers
15
and
17
generate an output signal at a ‘low’ logic level indicating that there is a defect.
The AND gate
19
receives the output signals of the first and second delayers
15
and
17
, performs an AND operation on the output signals, and generates the defect detection signal shown in
FIG. 2F
at an output terminal OUT.
The conventional defect detection circuit described above detects defects corresponding to a certain delay time Td generated by the microprocessor (not shown), regardless of a channel bit clock signal BCK commonly used as a reference signal when data recorded on the disc is reproduced. In the conventional defect detection circuit, the delay time Td with respect to the channel bit clock signal BCK, is equal for the inner and outer circumferences of the disc operating in a constant linear velocity (CLV) mode in which the same channel bit clock signal BCK is used during reproduction of data stored at the inner and outer circumferences. Accordingly, no errors are generated during reproduction.
However, a correct defect detection signal may not be generated during operation in a constant angular velocity (CAV) mode in which different channel bit clock signals BCK are used in the inner and outer circumferences of the disc. Namely, in CAV mode, since channel bit clock signals BCK having different frequencies are used for the inner and outer circumferences, a certain delay time Td is sensed differently for the inner and outer circumferences.
For example, assume the frequency of the channel bit clock signal BCK for reading data recorded in a central track of the disc to be 4.32 MHz in CAV mode. In this case, to read data recorded at the inner most circumference, a channel bit clock signal BCK of 2.16 MHz is used, which is half of 4.32 MHz. In the outer most circumference, the data is read by a channel bit clock signal BCK of 6.48 MHz, which is 1.5 times 4.32 MHz. Therefore, since the frequency of the channel bit clock signal BCK becomes larger in the outer circumference, a certain delay time Td generated in the microprocessor becomes shorter in the inner circumference, as compared to the outer circumference.
As a result, in a system operating in CAV mode, the conventional defect detecting circuit generates a certain delay time Td in the microprocessor. However, the system senses that the delay times Td having different lengths are generated during reproduction of data stored in the inner and outer circumferences of the disc. Accordingly, a correct defect detection signal is not generated.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a defect detecting circuit for an optical disc data reproduction system which correctly detects defects existing in an RF signal since delay time is controlled according to a varying channel bit clock signal in the optical disc reproducing system.
It is another object of the present invention to provide a defect detecting method performed in the defect detecting circuit of the optical disc reproducing system.
In a first aspect, the apparatus of the present invention is directed to a defect detection circuit in an optical disk data reproduction system including an optical pick up unit for generating an analog RF signal, for detecting defects in the RF signal. A comparator compares the RF signal voltage level with a first compare voltage having a predetermined voltage level and with a second compare voltage having a predetermined voltage level lower than the first compare voltage. In response to the RF signal voltage level being greater than that of the first compare voltage, a first comparison signal is generated. In response to the RF signal voltage level being less than that of the second compare voltage, a second comparison signal is generated. A defect detector receives the first and second comparison signals along with a channel bit clock signal. A defect detecting signal is generated when both the first and second comparison signals are deactivated for a time period that is greater in length than a first time duration. A
Huber Paul W.
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
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