Defect-and-failure-tolerant demultiplexer using series...

Details Defect-and-failure-tolerant demultiplexer using series... Defect-and-failure-tolerant demultiplexer using series...

2011-01-18

2011-01-18

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C326S014000

Reexamination Certificate

active

07872502

ABSTRACT:
One embodiment of the present invention is a method for constructing defect-and-failure-tolerant demultiplexers. This method is applicable to nanoscale, microscale, or larger-scale demultiplexer circuits. Demultiplexer circuits can be viewed as a set of AND gates, each including a reversibly switchable interconnection between a number of address lines, or address-line-derived signal lines, and an output signal line. Each reversibly switchable interconnection includes one or more reversibly switchable elements. In certain demultiplexer embodiments, NMOS and/or PMOS transistors are employed as reversibly switchable elements. In the method that represents one embodiment of the present invention, two or more serially connected transistors are employed in each reversibly switchable interconnection, so that short defects in up to one less than the number of serially interconnected transistors does not lead to failure of the reversibly switchable interconnection. In addition, error-control-encoding techniques are used to introduce additional address-line-derived signal lines and additional switchable interconnections so that the demultiplexer may function even when a number of individual, switchable interconnections are open-defective.

REFERENCES:
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patent: 7580026 (2009-08-01), Liu
patent: 2004/0051395 (2004-03-01), Brindle
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patent: 0431846 (1991-06-01), None
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EPO Examination Report, EP Application No. 07796813.9 issued by European Patent Office Sep. 21, 2010.
European Search Report, Application No. EP10156022.5-2215, dated Apr. 8, 2010.

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