Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate – Amorphous semiconductor
Reexamination Certificate
2000-09-15
2003-02-18
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Formation of semiconductive active region on any substrate
Amorphous semiconductor
C438S296000, C438S311000, C438S228000, C438S257000, C438S514000, C438S517000
Reexamination Certificate
active
06521515
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of manufacturing semiconductor devices and, more particularly, to an improved salicide process of forming metal silicide contacts.
BACKGROUND OF THE INVENTION
An important aim of ongoing research in the semiconductor industry is the reduction in the dimensions of the devices used in integrated circuits. Planar transistors, such as metal oxide semiconductor (MOS) transistors, are particularly suited for use in high-density integrated circuits. As the size of the MOS transistors and other active devices decreases, the dimensions of the source/drain regions and gate electrodes, and the channel region of each device, decrease correspondingly.
The design of ever-smaller planar transistors with short channel lengths makes it necessary to provide very shallow source/drain junctions. Shallow junctions are necessary to avoid lateral diffusion of implanted dopants into the channel, since such a diffusion disadvantageously contributes to leakage currents and poor breakdown performance. Shallow source/drain junctions, for example on the order of 1.000 Å or less thick are generally required for acceptable performance in short channel devices.
Metal silicide contacts are typically used to provide low resistance contacts to source/drain regions and gate electrodes. The metal silicide contacts are conventionally formed by depositing a conductive metal, such as titanium, cobalt, tungsten, or nickel, on the source/drain regions and gate electrodes by physical vapor deposition (PVD), e.g. sputtering or evaporation; or by a chemical vapor deposition (CVD) technique. Subsequently, heating is performed to react the metal with underlying silicon to form a metal silicide layer on the source/drain regions and gate electrodes. The metal silicide has a substantially lower sheet resistance than the silicon to which it is bonded. Selective etching is then conducted to remove unreacted metal from the non-silicided areas, such as the dielectric sidewall spacers. Thus, the silicide regions are aligned only on the electrically conductive areas. This self-aligned silicide process is generally referred to as the “salicide” process.
A portion of a typical semiconductor device
40
is schematically illustrated in FIG.
1
A and comprises a silicon-containing substrate
4
with source/drain
30
regions formed therein. Gate oxide
10
and gate electrode
12
are formed on the silicon-containing substrate
4
. Sidewall spacers
14
are formed on opposing side surfaces
13
of gate electrode
12
. Sidewall spacers
14
typically comprise silicon based insulators, such as silicon nitride, silicon oxide, or silicon carbide. The sidewall spacers
14
mask the side surfaces
13
of the gate
12
w hen metal layer
22
is deposited, thereby preventing silicide from forming on the gate electrode side surfaces
13
.
After metal layer
22
is deposited. heating is conducted at a temperature sufficient to react the metal with underlying silicon in the gate electrode
12
and substrate surface
5
to form conductive metal silicide contacts
24
(FIG.
1
B). After the metal silicide contacts
24
are formed, the unreacted metal
22
is removed by etching, as with a wet etchant, e.g., an aqueous H
2
O
2
/NH
4
OH solution. The sidewall spacer
14
, therefore, functions as an electrical insulator separating the silicide contact
24
on the gate electrode
12
from the metal silicide contacts
24
on the source/drain regions
30
, as shown in FIG.
1
B.
Various metals react with Si to form a silicide, however, titanium (Ti) and cobalt (Co) are currently the most common metals used to create silicides (TiSi
2
, CoSi
2
) when manufacturing semiconductor devices utilizing salicide technology.
Use of a TiSi
2
layer imposes limitations on the manufacture of semiconductor devices. A significant limitation is that the sheet resistance for lines narrower than 0.35 micrometers is high, i.e., as TiSi
2
is formed in a narrower and narrower line, the resistance increases. Another significant limitation is that TiSi
2
initially forms a high resistivity phase (C
49
), and transformation from C
49
to a low resistivity phase (C
54
) is nucleation limited, i.e., a high temperature is required to effect the phase change.
Cobalt silicide, unlike TiSi
2
, exhibits less linewidth dependence of sheet resistance. However, CoSi
2
consumes significant amounts of Si during formation, which increases the difficulty of forming shallow junctions. Large Si consumption is also a concern where the amount of Si present is limited, for example, with silicon on insulator (SOI) substrates. Without enough Si to react with Co to form CoSi
2
, a thin layer of CoSi
2
results. The thickness of the silicide layer is an important parameter because a thin silicide layer is more resistive than a thicker silicide layer of the same material, thus a thicker silicide layer increases semiconductor device speed, while a thin silicide layer reduces device speed.
Recently, attention has turned towards using nickel to form NiSi utilizing salicide technology. Using NiSi is advantageous over using TiSi
2
and CoSi
2
because many limitations associated with TiSi
2
and CoSi
2
are avoided. When forming NiSi, a low resistivity phase is the first phase to form, and does so at a relatively low temperature. Additionally, nickel (Ni), like Co, diffuses through the film into Si, unlike Ti where the Si diffuses into the metal layer. Diffusion of Ni and Co through the film into Si prevents bridging between the silicide layer on the gate electrode and the silicide layer over the source/drain regions. The reaction that forms NiSi requires less Si than when TiSi
2
and CoSi
2
are formed. Nickel silicide exhibits almost no linewidth dependence of sheet resistance. Nickel silicide is normally annealed in a one step process, versus a process requiring an anneal, an etch, and a second anneal, as is normal for TiSi
2
and CoSi
2
. Nickel silicide also exhibits low film stress, i.e., causes less wafer distortion.
Although the use of NiSi in salicide technology has certain advantages over utilizing TiSi
2
and CoSi
2
, there are problems using NiSi in certain situations. Forming NiSi on doped, crystallized Si usually produces a smooth interface between the NiSi layer and the doped, crystallized Si layer. However, when crystallized Si is doped with arsenic (As), a rough interface between the NiSi and the doped, crystallized Si forms, which leads to certain problems.
FIG. 2
illustrates the degree of interface
36
roughness between a conventional nickel silicide (NiSi) contact
24
and arsenic doped source/drain region
30
. In this system, the mean peak to valley interface roughness height d is about 300 Å to about 400 Å. This large degree of interface roughness can cause a variety of electrical problems such as spiking and increased junction leakage. The interface roughness could penetrate all the way through the source/drain region in a shallow junction device, causing a local short circuit, thereby resulting in junction leakage. In order to prevent these problems, a thinner metal layer can be deposited, thereby resulting in a thinner silicide layer, or the depth of source/drain junction can be increased. However, neither of these approaches is satisfactory: the former approach would result in higher sheet resistance and a slower semiconductor device, and the latter approach runs counter to the trend toward smaller device dimensions, both vertically, and laterally, in order to increase switching speeds.
Interface roughness becomes more pronounced as the concentration of the dopant increases. In an As doped device with NiSi contacts, interface roughness is especially a problem where the peak concentration of the doped arsenic is in the vicinity of the upper surface of the source/drain regions. In a typical arsenic doped MOS device the arsenic ions will be implanted with an energy and dose of 10 to 20 keV and 1×10
15
to 6×10
15
ions/cm
2
, which results in a peak arsenic concentration at about 200 Å t
Advanced Micro Devices , Inc.
Smith Matthew
Yevsikov V.
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