Deep well implant structure providing latch-up resistant...

Details Deep well implant structure providing latch-up resistant... Deep well implant structure providing latch-up resistant...

2006-01-31

2006-01-31

Dang, Phuc T. (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

C257S509000, C438S199000

Reexamination Certificate

active

06992361

ABSTRACT:
A CMOS semiconductor product employs a first doped well of a first polarity and a second doped well of a second polarity opposite the first polarity, each formed laterally separated within a semiconductor substrate. The first doped well is further embedded within a third doped well of the second polarity that further separates the first doped well from the second doped well. The third doped well provides latch-up resistance for a pair of MOS transistors formed within the first doped well and the second doped well.

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patent: 6329233 (2001-12-01), Pan et al.
patent: 6359316 (2002-03-01), Voss et al.

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