Deep trench etching process using CCl.sub.2 F.sub.2 /Ar and CCl.

Details Deep trench etching process using CCl.sub.2 F.sub.2 /Ar and CCl. Deep trench etching process using CCl.sub.2 F.sub.2 /Ar and CCl.

1983-12-12

1984-10-09

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156628, 156646, 156651, 1566591, 156657, 1566611, 156662, 204192E, 252 791, H01L 21306, B44C 122, C03C 1500, C03C 2506

Patent

active

044759827

ABSTRACT:
This invention relates to a process for forming deep trenches in semiconductor substrates by Reactive Ion Etching and more particularly relates to an etching process which prevents lateral etching or "blooming" in a heavily doped semiconductor region which is sandwiched by upper and lower lightly doped regions of semiconductor. Still more particularly it relates to an RIE process wherein the upper region is reactively ion etched in an atmosphere of CCl.sub.2 F.sub.2 and argon to at least a portion of the thickness of the upper region and wherein any remaining thickness of the upper region, the heavily doped region and at least a portion of the lower region are reactively ion etched in an atmosphere of CCl.sub.2 F.sub.2 and oxygen to provide a trench with uniform sidewalls.

REFERENCES:
IBM Technical Disclosure Bulletin, vol. 25, No. 8, Jan. 1983, Method for Forming Vertical Walled Trenches in Silicon Substrates Using Reactive Sputter Etching by J. S. Lechaton et al., pp. 408-409.
IBM Technical Disclosure Bulletin, vol. 22, No. 5, Oct. 1979, Reactive Ion Etching of Silicon by P. M. Schaible et al., p. 1819.
IBM Technical Disclosure Bulletin, vol. 21, No. 7, Dec. 1978, pp. 2814-2815, "Reactive Ion Etching of Silicon" by P. M. Schaible et al.
IBM Technical Disclosure Bulletin, vol. 22, No. 10, Mar. 1980, pp. 4516-4517, "Chromium as an RIE Etch Barrier" J. E. Hitchner et al.

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