Deep trench capacitor for SOI CMOS devices for soft error...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE27092, C257SE21647, C438S243000

Reexamination Certificate

active

07989865

ABSTRACT:
A semiconductor structure is disclosed. The semiconductor structure includes an active semiconductor layer, a semiconductor device having a gate disposed on top of the active semiconductor layer, and source and drain regions and a body/channel region disposed within the active semiconductor layer, an insulator layer having a first and second side, the first side being adjacent to the active semiconductor layer, a substrate disposed adjacent to the second side of the insulator layer, a deep trench capacitor disposed under the body/channel region of the semiconductor device. The deep trench capacitor electrically connects with and contacts the body/channel region of the semiconductor device, and is located adjacent to the gate of the semiconductor device. The semiconductor structure increases a critical charge Qcrit, thereby reducing a soft error rate (SER) of the semiconductor device.

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Wu, B. “Pillar Dram Cell With Dual Channels and an Underneath Trench-in-Trench Capacitor Built on Soi Structure”, IBM Technical Disclosure Bulletin, Nov. 1993, pp. 141-144.

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