Deep submicron silicide blocking

Details Deep submicron silicide blocking Deep submicron silicide blocking

2001-10-16

2003-07-01

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S655000, C438S303000, C438S304000, C438S305000, C438S306000, C438S307000

Reexamination Certificate

active

06586332

ABSTRACT:

FIELD
This invention relates to the field of integrated circuit processing. More particularly, this invention relates to a method for blocking silicide formation on structures such as island resistors in deep submicron integrated circuits.
BACKGROUND
There is continual pressure for integrated circuits to be increasingly faster and increasingly more powerful. Both of these objectives tend to be influenced by the size of the integrated circuits. By fabricating smaller integrated circuits, electrical pathways are shorter and more devices are formed within a given space, which tends to result in a faster, more powerful integrated circuit.
However, as integrated circuits become smaller, the devices within integrated circuits also become smaller. As lateral integrated circuit device geometries continue to shrink, it often is desirable to commensurately shrink certain vertical geometries of the integrated circuits as well. As the various layers and structures also become thinner, it tends to become increasingly important to control the formation of the layers and structures, because there tends to be less tolerance to variation in the thickness of a relatively thinner structure than in the thickness of a relatively thicker structure.
When fabricating integrated circuits such as complimentary metal oxide semiconductor devices, it is typically desirable to form the source and the drain regions with shallow junction depths in the substrate. The junction depths for a deep submicron device are typically less than about one thousand angstroms. However, there are other design goals that compete with the design goal of forming source and drain regions with shallow junction depths. For example, silicide blocking polysilicon and island resistors, called block resistors herein, are typically formed on the substrate to perform functions such as impedance matching, data conversion, and bias functions.
In order to form silicide block resistors on a substrate, material such as oxide is deposited on the surface of the substrate and then selectively removed. Those areas in which the oxide is removed are exposed to a metal deposition and silicided, and those areas in which the oxide remains are not silicided. During the removal of the oxide blocking material, other structures or devices on the substrate such as trench isolation areas also tend to have material removed. Removal of the oxide from the trench isolation areas typically creates additional recesses, which tend to cause increased junction leakage current.
Thus, there is a need for a process for forming silicide block resistors in a substrate, where any material removed from the isolation areas is reduced.
SUMMARY
The above and other needs are met by a method for blocking formation of a reacted metal layer on a structure in an integrated circuit. The integrated circuit has a source region, a drain region, a gate, an isolation area formed of a material, and a protective layer formed of substantially the same material as the isolation area. The protective layer overlies at least the source region and the drain region. The method is accomplished while reducing an amount of the material of the isolation area that is removed when the material of the protective layer is removed.
A blocking layer is deposited on the integrated circuit. The blocking layer is formed of a material that is substantially different from the material of the isolation area and the protective layer. The blocking layer is patterned to selectively cover portions of the blocking layers that overlie at least the structure and selectively expose portions of the blocking layer that overlie at least the source region, the drain region, and the gate. The exposed portions of the blocking layer are etched with an etchant to substantially remove the exposed portions of the blocking layer, and to expose portions of the protective layer. The etchant etches the blocking layer at a substantially greater rate than the protective layer.
The exposed portions of the protective layer are etched for a period of time that is just sufficient to remove the exposed portions of the protective layer, but not sufficient to substantially remove any of the material of the isolation area. Portions of the integrated circuit are thereby exposed, including at least the source region, the drain region, and the gate. Metal is deposited on the exposed portions of the integrated circuit. The metal is reacted with at least the source region, the drain region, and the gate to form the reacted metal layer, and unreacted metal is removed from other exposed portions of the integrated circuit and the blocking layer.
Thus, by forming the blocking layer of a material that is substantially different from the material of the protective layer and the isolation structure, the thickness of the blocking layer can be removed without etching the material of the protective. Then when the protective layer is removed, a thinner layer of material is removed, which provides for a greater degree of control of over etching of the protective layer. In this manner, the amount of material that is removed from the isolation structures is preferably reduced. By protecting the isolation areas from over etching and thereby reducing removal of material from the isolation areas, the shallow junction source and drain regions may be fully silicided without a substantial increase in leakage current.
In various preferred embodiments of the invention, the substrate is silicon and the protective layer is silicon oxide. The blocking layer is preferably deposited by plasma enhanced chemical vapor deposition using an alkyl silane base precursor. In a preferred embodiment, the blocking layer is amorphous silicon carbide and the step of patterning the blocking layer further comprises depositing a photoresist layer and a bottom antireflection coating, exposing the photoresist layer, and developing the photoresist layer. In an alternate embodiment, the blocking layer is amorphous silicon oxy carbide and the step of patterning the blocking layer further comprises depositing a photoresist layer, exposing the photoresist layer, and developing the photoresist layer, wherein the blocking layer serves as an antireflection coating layer. In a preferred embodiment, the etching process of the protective layer comprises a wet etch using hydrofluoric acid. The etching process of the blocking layer preferably comprises a plasma etch.


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