Deep sub-micron metal etch with in-situ hard mask etch

Details Deep sub-micron metal etch with in-situ hard mask etch Deep sub-micron metal etch with in-situ hard mask etch

1998-12-16

2001-02-27

Powell, William (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C216S047000, C216S075000, C438S720000, C438S742000

Reexamination Certificate

active

06194323

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuits and semiconductor devices and methods for making same.
BACKGROUND OF THE INVENTION
As the width of the metal lines in silicon and other semiconductor devices shrink to 0.30 micron and lower, the thickness of photoresist (PR) required to pattern the metal lines present as conductors needs to decrease substantially to enhance the resolution. Typically, photoresist is applied directly on top of a metal layer to be etched. However, simply decreasing the thickness of photoresist results in insufficient photoresist being present to obtain a correctly shaped metal line following metal etching. While systems of photoresist of at least 1 micron in thickness, and silicon nitride hardmask of about 300 nm in thickness are know, they are not thin enough and do not have the etch selectivity to support 0.2 micron design rule integrated circuit production.
SUMMARY OF THE INVENTION
The invention includes a process for the production of semiconductor devices comprising the steps of depositing a metal layer on a semiconductor substrate, depositing a hardmask layer on said metal layer, depositing a photoresist on said hardmask layer, patterning said photoresist, thereby exposing and patterning portions of said hardmask layer, etching said exposed portions of said hardmask layer with a hardmask etchant, thereby exposing and patterning portions of said metal layer, optionally removing said photoresist, and etching said exposed portions of said metal layer with a metal etchant. The invention includes semiconductor devices made by said process.


REFERENCES:
patent: 5950106 (1999-09-01), May et al.
patent: 6020269 (2000-02-01), Wang et al.

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