Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Total dielectric isolation
Patent
1995-03-29
1998-08-18
Niebling, John
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Total dielectric isolation
438412, 438425, H01L 2176
Patent
active
057958106
ABSTRACT:
A method of making an integrated circuit in semiconductor on insulator material and the circuit which comprises providing a semiconductor on insulator structure having a device layer, preferably silicon, and an electrically insulating layer, the device layer being in contact with one surface of the electrically insulating layer. An underlayer is provided which contacts the opposing surface of the electrically insulating layer. The structure is then patterned and trenches are etched to expose a surface of the underlying layer and to form mesas extending from the underlying layer. Ions can now optionally be implanted into selected regions of the underlying layer. A dielectric is provided between the mesas extending to or into the substrate and fabrication of the integrated circuit is then completed. The dielectric can be a thermal oxide at the exposed surface with a dielectric over the thermal oxide. Prior to formation of the thermal oxide, a sidewall dielectric can be formed over the electrically conductive layer. The exposed surface of the dielectric between the mesas is preferably substantially coplanar with the top surface of the mesas.
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Brady III W. James
Donaldson Richard L.
Mulpuri S.
Niebling John
Texas Instruments Incorporated
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