Decoupling floating point linear address

Details Decoupling floating point linear address Decoupling floating point linear address

2005-08-23

2005-08-23

Sparks, Donald (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

In response to microinstruction

C711S203000, C711S204000, C711S213000, C711S214000, C712S217000, C712S218000, C712S219000, C712S222000, C712S223000, C712S224000, C712S229000

Reexamination Certificate

active

06934828

ABSTRACT:
A technique is described to reduce the complexity of floating point linear address (FLA) maintenance in a superscalar processor by coupling FLA updates when floating point data is stored instead of when floating point addresses are stored.

REFERENCES:
patent: 4763294 (1988-08-01), Fong
patent: 5559977 (1996-09-01), Avnon et al.
patent: 5579527 (1996-11-01), Chin et al.
patent: 5581778 (1996-12-01), Chin et al.
patent: 5721857 (1998-02-01), Glew et al.
Clouser et al, Jul. 1999, IEEE Journal of solid-state-circuits, vol. 34, 1026-1029.

Affiliated with

Also associated with

Rating

Decoupling floating point linear address does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Decoupling floating point linear address, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Decoupling floating point linear address will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3506250