Decoupling capacitors for thin gate oxides

Details Decoupling capacitors for thin gate oxides Decoupling capacitors for thin gate oxides

1999-12-22

2004-12-07

Kang, Donghee (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S391000, C257S402000, C257S313000, C438S217000, C438S288000, C438S299000

Reexamination Certificate

active

06828638

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field of the Invention
The present invention relates to integrated circuits and, more particularly, to decoupling capacitors in integrated circuits.
2. Background Art
Decoupling capacitors (“decaps”) are used in integrated circuit (IC) design for noise decoupling. Indeed, they are heavily used in virtually all IC's. One type of semiconductor capacitor is called a MOS-C or metal oxide semiconductor capacitor. The MOS-C has two terminals separated by a dielectric region (which includes at least an insulator, such as gate oxide). One of the terminals is the gate and the other is the body (and perhaps source and drain diffusions). Another type of semiconductor capacitor is using a field effect transistor (FET) such as an n-channel metal oxide semiconductor FET (NMOSFET) or a p-channel metal oxide semiconductor FET (NMOSFET). One of the terminals is the gate and the other terminal is the source, drain, and body. The terminals are separated by a dielectric (which includes at least an insulator, such as gate oxide). A difference between a MOS-C and a FET capacitor are that with a FET, the source and drains have a different polarity type than does the body. With a MOS-C, the source/drain diffusions (if present) have the same polarity as the body. The behavior of capacitors in integrated circuits is described in R. Pierret et al., “Field Effect Devices,” (Addison-Wesley, 2nd Ed. 1990), pp. 47-59; and in N. Weste et al., “Principles of CMOS VLSI Design,” (Addison-Wesley, 2nd Ed. 1993), pp. 180-82.
Other decoupling capacitors such as a capacitor sandwiched in between two metal lines with a high dielectric constant insulator are also possible. However, the material challenge and integration in today's MOS technology will be very difficult.
The capacitance C of a capacitor is given by the equation C=&egr; A/d, were &egr; is the dielectric constant, A is the area, and d is the distance. In the design IC's, it is desirable to make the dimensions of the components small. Accordingly, over the years, the area A of the capacitors has become smaller, while the distance d between electrodes has also become smaller. Currently used capacitor structures generally work fairly well with oxides that do not leak. The current decoupling capacitors structures have voltages applied to keep the MOS-C in inversion resulting in maximum per unit area capacitance value, with good high frequency response time, and low series resistance. As process technology scales, gate oxide thickness also scales in order to maintain transistors with good drive current capabilities and a good short channel behavior. As gate oxides continue to scale (e.g., below
30
A), this capacitive configuration results in high leakage conduction through oxide (e.g., elevated tunneling leakage).
SUMMARY
In some embodiments, the invention includes a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage.
Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body ; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.
Additional embodiments are described and claimed.


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N. Weste et al., “Principles of CMOS VLSI Design” (Addison-Wesley, 2nd Ed. 1993), pp. 41-51 and 180-187.
R. Pierret, “Field Effect Devices, vol. IV of Modular Series on Sold State Devices” (Addison-Wesley, 2nd Ed. 1990), pp. 47-59.

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