Decoupled reset dynamic logic circuit

Details Decoupled reset dynamic logic circuit Decoupled reset dynamic logic circuit

1998-06-16

2000-10-17

Santamauro, Jon

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 27, 326121, H03K 190948

Patent

active

061337595

ABSTRACT:
A dynamic logic circuit is implemented which decouples the reset of the output from the reset of the evaluation node. An N-tree logic circuit generates a logical output signal in response to a first set of input signals. The output signal is coupled to a gate of a first n-type field effect transistor (NFET) of a parallel coupled pair of NFET devices. The parallel drains are coupled to an output of the dynamic logic circuit and the parallel sources are coupled to ground. The gate of the second NFET device of the pair is coupled to the junction of a source and drain, respectively, of a series connected p-type field effect transistor (PFET) device, and a third NFET device. The third NFET device has a source coupled to ground, and the PFET device has a drain coupled to a voltage supply. Gates of the PFET device and the third NFET device are connected together and receive a logic signal whereby the output of the dynamic logic circuit may be reset.

REFERENCES:
patent: 4401903 (1983-08-01), Iizuka
patent: 5208489 (1993-05-01), Houston
patent: 5541537 (1996-07-01), Kim et al.
patent: 5831452 (1998-11-01), Nowak et al.
patent: 5841300 (1998-11-01), Murabayashi et al.
Horenstein, Mark. Microelectronic Circuits & Devices. Prentice-Hall, pp. 723-725, 1990.

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