Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-11-15
2003-06-03
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06574782
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to methods and systems that calculate (“extract”) the parasitic capacitance that will be exhibited by an integrated circuit design and more particularly to an improved method of determining parasitic capacitance that reduces the computational burden when compared to conventional systems.
2. Description of the Related Art
With the high cost of tooling and manufacturing integrated circuit devices, designers prefer to prepare and test models of the integrated circuit prior to actual manufacturing production. An actual physical model of the integrated circuit structure can be constructed. However, it is preferable to evaluate the design itself to determine if it complies with various rules (such as ground rules, minimum spacing rules, etc.) and to estimate whether the circuit will perform as the designers intended. This testing is preferably performed by software utilizing a computer simulation. With such a system, a physical model does not need to be created and the design can be easily incrementally improved as problems are revealed during the testing stage.
One aspect of testing integrated circuit designs involves extracting the capacitance between various conductors and insulators within the integrated circuit. Many integrated circuit structures comprise multi-layer or laminated structures that have multiple parallel wiring levels that are interconnected with conductive vias. Insulators prevent short circuits between adjacent layers and between wiring within a single layer. These various conductors and insulators have a capacitance value that changes depending upon the size and number of wires and the thickness of the insulators.
When evaluating the capacitance of a single wire of a very large scale integrated (VLSI) design belonging to a single level, most wires above and below will be orthogonal (perpendicular in the xy-plane) to the given wire. Typically, a parasitic capacitance extraction program will find all of the overlapping wires above and below the given wire to get a reasonable approximation of the capacitive coupling above and below. Lateral coupling is typically found by measuring the spacing to the nearest neighboring wires of the same level possibly including the effect of the nearest wires above and below the lateral coupling wire pair.
All these small capacitance contributions are then added to result in capacitances per wire segments. However, the calculations required to extract the capacitance of each wiring element in such conventional systems produces a large burden upon the computing overhead and results in a lengthy computing process. Therefore, there is a need to reduce the computational overhead and excessive computational time associate with conventional capacitance extraction systems.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for extracting parasitic capacitance from a multi-layer wiring structure that creates, for each wiring layer in a wiring structure, a wiring density map and measures a plurality of metal segments in a wiring layer to determine an area occupied by the metal segments. The invention calculates an up area capacitance component for each of the metal segments by multiplying the area occupied by the metal segments by a wiring density from the wiring density map of an overlying wiring layer over the metal segments and by a capacitance coefficient of the overlying wiring layer. To calculate the down area capacitance component for each of the metal segments, the invention multiplies the area occupied by the metal segments by a wiring density, from the wiring density map of an underlying wiring layer under the metal segments and by a capacitance coefficient of the underlying wiring layer. The invention combines the up area capacitance component and the down area capacitance component to form a vertical coupling capacitance component for each of the metal segments.
The invention also calculates an up fringe capacitance component using an average distance between the overlying layer and the metal segments and a distance between adjacent metal segments in the wiring layer. The invention similarly calculates a down fringe capacitance component using an average distance between the underlying layer and the metal segments and a distance between adjacent metal segments in the wiring layer. The invention ties the vertical capacitance component, the up fringe capacitance component and the down fringe capacitance component to ground to produce an overall area capacitance.
The invention can also calculate a lateral coupling capacitance using an average distance between the overlying layer and the metal segments, an average distance between the underlying layer and the metal segments, and a distance between adjacent metal segments in the wiring layer. The invention ties the coupling capacitance to networks within the wiring layer to produce an overall coupling capacitance. The invention combines the overall area capacitance and the overall coupling capacitance with a resistance of each of the metal segments to produce a distributed coupled network capacitance.
In another embodiment, the invention partitions the wiring layer, the overlying layer, and the underlying layer into equal two-dimensional areas wherein the calculating of the up area capacitance component, the down area capacitance component, the fringe up capacitance component, the fringe down capacitance component and the lateral capacitance component for the metal segments within each of the areas. For metal segments that occupy more than one of the two-dimensional areas, the invention divides the metal segments into a plurality of conductive segments, each occupying at least a portion of the two-dimensional areas and determines the overall area capacitance. The overall coupling capacitance for each of the conductive segments are calculated as segment coupling capacitances. The invention sums the segment coupling capacitances to produce an overall coupling capacitance of each of the metal segments.
The inventive system for extracting parasitic capacitance from a multi-layer wiring structure includes a mapping unit adapted to partition a first layer and a second layer of the wiring structure into a plurality of two-dimensional areas (the first layer is adjacent the second layer), a density scale adapted to determine a wiring density of a first two-dimensional area in the first layer, and a capacitance coupler adapted to determine an average coupling capacitance coefficient of the first two-dimensional area relative to a corresponding second two-dimensional area in the second layer. A size calculator measures a size of a conductive element within the second two-dimensional area and a mathematical unit multiplies the size of the conductive element by the wiring density and by the coupling capacitance coefficient to determine a coupling capacitance between the first layer and the second layer for the conductive element.
The capacitance coupler determines a second average coupling capacitance coefficient of the second two-dimensional area relative to a corresponding third two-dimensional area in a third layer. The third layer is adjacent the second layer and on an opposite side of the second layer from the first layer. The density scale further determines a wiring density of the third area, and the mathematical unit further multiplies the size of the conductive element by the wiring density of the third area and by the second average coupling capacitance coefficient to produce a second coupling capacitance. The mathematical also combines the coupling capacitance and the second coupling capacitance. Further, the first area, the second area, and the third area have identical dimension and the mathematical unit determines the coupling capacitance of all conductive elements in the second area.
If the conductive element occupies more than one area in the second layer of the wiring structure, the mapping unit divides the conductive element
Dewey, III L. William
Habitz Peter A.
Mitchell Thomas G.
International Business Machines - Corporation
Kotulak, Esq. Richard M.
Levin Naum
McGinn & Gibb PLLC
Siek Vuthe
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