Decoupled address and data access to an SDRAM

Details Decoupled address and data access to an SDRAM Decoupled address and data access to an SDRAM

1998-09-18

2002-07-09

Kim, Matthew (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C710S058000, C710S316000, C711S147000, C711S202000

Reexamination Certificate

active

06418518

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to accessing an SDRAM, and in particular to decoupling address and data paths to an SDRAM.
BACKGROUND OF THE INVENTION
Synchronous dynamic random access memory (SDRAM) is a type of memory which is used in a wide variety of applications. An SDRAM may be divided into a plurality of banks. Each bank is further divided into a plurality of pages. In a typical SDRAM with a 48-bit wide data bus and an 8-bit wide column address, a page has 1.5 Kbytes of memory. To access a page, the SDRAM must perform pre-charge and activate operations. The pre-charge and activate operations. cause some delay in accessing a memory location, however sequential accesses to the same page do not require additional pre-charge and activate operations. Nonetheless, to access a new page, the SDRAM must perform pre-charge and activate operations on the new page. These pre-charge and activate operations also causes some delay in accessing the desired memory location. To speed access to data stored in the SDRAM, data which will be accessed together should be stored on the same page. This acts to minimize the number of pre-charge and activate delays.
Since each bank includes a plurality of pages, the access of a memory location in a new page may or may not occur within the same bank. If the access of a memory location does cross a bank boundary and therefore also a page boundary, the pre-charge operation may begin before completion of the previous access. On the other hand, if the access of a memory location crosses a page boundary but does not cross a bank boundary, the pre-charge operation may not begin until after the completion of the previous access.
In some applications, the memory manager (or control process) which stores data to the SDRAM operates based upon one clock (i.e., in a first clock domain) and the SDRAM operates based upon another clock (i.e., in a second clock domain). These clocks may be asynchronous and may operate at different frequencies. When the memory manager attempts to access the SDRAM both address and data information must cross the clock domain boundary. In other words, both the address and data information must be synchronized from the first clock to the second clock. The synchronization of address and data information across the clock domain boundary delays memory access.
One application, which uses an SDRAM in a different clock domain, involves network switches which temporarily store packet data. For example, network switches are frequently used on Ethernet networks to connect multiple sub-networks. A switch receives packet data from one sub-network and passes that packet data onto another sub-network. Upon receiving a packet, a network switch may divide the packet data into a plurality of sub-packets or cells. Each of the cells includes additional header data. As is well known in the art, Ethernet packet data has a maximum size of approximately 1.5 Kbytes. With the additional header data associated with the cells, a packet of data has a maximum size of under 2 Kbytes.
After dividing the packet data into cells, the network switch may temporarily allocate a memory buffer in the SDRAM to store the packet before retransmission. The address and packet data are translated across the clock domain boundary to the SDRAM. The packet data is then stored in the memory buffer. For retransmission, the switch again accesses the SDRAM to retrieve the packet data. Both the storage and retrieval of data from the SDRAM introduce access delays.
In addition, for a 48-bit wide SDRAM with an 8-bit wide column address, the page size is 1.5 Kbytes. Accordingly, a 2-Kbyte Ethernet packet including cell headers will cross a page boundary. This introduces further access delays. on heavily-trafficked high-speed networks such delays can have a damaging effect on network performance.
Accordingly, an SDRAM is desired which may be configured as a buffer for storing Ethernet packet data. The SDRAM may operate in a clock domain different than a control process. Nonetheless, the SDRAM should operate to minimize access delays.
SUMMARY OF THE INVENTION
In one preferred embodiment, an address translation circuit for mapping address information to an SDRAM includes a buffer manager interface and a translation circuit. The buffer manager interface is configured to receive address information from a buffer manager. The buffer manager allocates a plurality of buffers each having a start address and an end address related therewith. The translation circuit is operationally coupled with the buffer manager interface. The translation circuit maps the start address of each of the plurality of buffers to a first bank and maps the related end address to a second bank, different than the first bank.


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