Decomposer for parallel turbo decoding, process and...

Details Decomposer for parallel turbo decoding, process and... Decomposer for parallel turbo decoding, process and...

2006-08-22

2006-08-22

Torres, Joseph (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S701000

Reexamination Certificate

active

07096413

ABSTRACT:
A decoder for access data stored in n memories comprises a function matrix containing addresses of the memory locations at unique coordinates. A decomposer sorts addresses from coordinate locations of first and second m×n matrices, such that each row contains no more than one address from the same memory. Positional apparatus stores entries in third and fourth m×n matrices identifying coordinates of addresses in the function matrix such that each entry in the third matrix is at coordinates that matches corresponding coordinates in the first matrix, and each entry in the fourth matrix is at coordinates that matches corresponding coordinates in the second matrix. The decoder is responsive to entries in the matrices for accessing data in parallel from the memories.

REFERENCES:
patent: 4700294 (1987-10-01), Haynes
patent: 5550774 (1996-08-01), Brauer et al.

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