Decoding unit and preprocessing unit implemented according...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S755000

Reexamination Certificate

active

07603607

ABSTRACT:
In processing of calculating outer value log-ratio αmn by a row processing unit performing an operation on rows of a parity check matrix, a minimum absolute value and a second minimum absolute value out of data utilized for the row processing are stored. When the data to be processed matches with the minimum value, the second minimum value is outputted. When the data to be processed does not match with the minimum value, the minimum value is output. Thus, it is possible to simplify a construction of a portion for executing Min operation of obtaining a minimum value in the processing of a decoding operation according to a min-sum decoding algorithm. It is possible to reduce a scale of circuitry for decoding low density parity check codes.

REFERENCES:
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patent: 7039846 (2006-05-01), Hewitt et al.
patent: 7219288 (2007-05-01), Dielissen et al.
patent: 2006/0156167 (2006-07-01), Dielissen et al.
patent: 2004-186940 (2004-07-01), None
patent: 2006-508577 (2006-03-01), None
patent: WO 2004-049578 (2004-06-01), None
Sae-Young Chung et al., “On the Design of Low-Density Parity-Check Codes within 0.0045 dB of the Shannon Limit”, IEEE Communications Letters, vol. 5, No. 2, Feb. 2001, pp. 58-60.
Engling Yeo et al., “VLSI Architectures for Iterative Decoders in Magnetic Recording Channels”, IEEE Transactions on Magnetic, vol. 37, No. 2, Mar. 2001, pp. 748-755.
Tadashi Wadayama, “Introduction to Low Density Parity Check Codes and the Sum-Products Algorithm”, Technical Report of IEICE., MR 2001-83, Dec. 2001, The Institute of Electronics, Information and Communication Engineers.

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