Decoding techniques for read-only memory

Static information storage and retrieval – Read/write circuit – Including specified plural element logic arrangement

Reexamination Certificate

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C365S230020, C365S190000

Reexamination Certificate

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11363366

ABSTRACT:
A memory circuit includes a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of column sense logic units are also provided, corresponding to the bit line structures. Each of the column sense logic units includes a first logic gate and a second logic gate. The first logic gate has a first input connected with a first one of the bit lines and a second input connected with a second one of the bit lines. The second logic gate has a first input interconnected with a third one of the bit lines, and a second input interconnected with the second one of the bit lines.

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