Decoding system capable of charging protection for flash...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S355000, C257S324000, C257SE27103

Reexamination Certificate

active

07948035

ABSTRACT:
The present invention relates to a flash memory array. The flash memory array includes at least two word lines of gate electrode material. At least one of the word lines is connected through a first metal level to a discharge circuit, while other word line(s) may connect to a discharge circuit through a first and second metal level. The memory array further includes a shorting path between the word lines of the memory array. The shorting path is a high resistance layer of undoped gate electrode material. The resistance value of the gate electrode material is such that the word lines can be used to read, write, or erase without effecting each other, but that during the formation of a first metal level, as charges will build up on a first word line which requires a second metal level to connect to its discharge junction circuit, it will short the first word line to an adjacent second word line that has a connection to its junction circuit on the first metal level.

REFERENCES:
patent: 7713875 (2010-05-01), Brennan et al.
patent: 7750407 (2010-07-01), Zheng et al.

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