Decoding scheme for a stacked bank architecture

Details Decoding scheme for a stacked bank architecture Decoding scheme for a stacked bank architecture

2001-06-25

2003-08-05

Ho, Hoai (Department: 2818)

Static information storage and retrieval

Read/write circuit

Simultaneous operations

C365S230030, C365S230060

Reexamination Certificate

active

06603683

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory architecture and, more particularly, to an address decoding scheme for a stacked-bank memory architecture.
2. Background Description
There is an ever increasing need for access speed and throughput in a memory device to meet the demands of ever faster generations of processors. One common type of memory device used with processors is a dynamic random access memory (DRAM). DRAMs comprise an array of individual memory cells. The memory array consists of a multitude of rows and columns, where the intersection of each row and column defines a memory cell location address. Typically, each DRAM memory cell comprises a capacitor for holding a charge and an access transistor for accessing the capacitor for altering or sensing the charge. The charge is representative of a data bit and can be either high voltage or low voltage (representing, e.g., a logical “1” or a logical “0”, respectively). Data can be stored in memory during write operations or read from memory during read operations.
The capacitor is charged while data is written into DRAM in a write operation, and the amount of charge stored in the capacitor is sensed to estimate the logic states of the memory cells while data is read from memory cells in a subsequent read cycle. However, capacitors are subject to charge leakage and a typical DRAM needs so-called refresh operation cycles, during which the DRAM can replace charge in accordance with stored data.
Refresh, read, and write operations in conventional DRAMs are typically performed for all cells in one row simultaneously. Data is read from a memory cell by activating a row, referred to as a word line, which couples all memory cells corresponding to that row to digit or bit lines which define the columns of the array. When a particular word line is activated, sense amplifiers detect and amplify the data present on an active bit/column line. In order to access a memory cell in the memory array, the DRAM operating system selects the particular row and column corresponding to that bit, and the sense amplifier determines whether a “1” or a “0” has been stored in the memory location.
In order to improve access speed and cycle time of a DRAM, a proposal was made to reduce a memory array size; a so called “micro-cell architecture”. The goal of this approach is to significantly reduce the length of each word line and the number of word lines per each memory cell array to reduce the capacitance load presented thereby. To achieve this goal, it has been widely adopted to arrange the memory cells of a DRAM into operative units, also referred to as “banks” to form “a multi-bank structure”. Conventionally, a DRAM chip for a stand alone or embedded DRAM design may comprise two to sixteen banks. Some memories are capable of simultaneously accessing four banks for a read, write or refresh operation.
An example of this type of architecture in shown in
FIG. 1
, which illustrates a schematic diagram of a semiconductor memory chip
1
divided into two memory array blocks
10
and a spine area
12
.
It is to be understood that
FIGS. 1 and 2
are largely generic, highly schematic and arranged to facilitate an understanding of the problems addressed by the invention. Therefore, while
FIGS. 1 and 2
do not explicitly illustrate the invention, no portion
FIG. 1
or
2
is admitted to be prior art in regard to the present invention. Accordingly,
FIGS. 1 and 2
have been designated as “Related Art”.
In
FIG. 1
, a main address bus or a global address bus is normally arranged within the spine area
12
and transfers memory cell addresses and data for read/write/refresh operations in each bank. In
FIG. 1
, each memory array block
10
is divided into eight banks. The odd number memory banks (banks
1
,
3
,
5
,
7
,
9
,
11
,
13
and
15
) are arranged in the memory array block
10
on the left of the spine area
12
, and the even number memory banks (bank
2
,
4
,
6
,
8
,
10
,
12
,
14
and
16
) are arranged in the memory array block
10
on the right of the spine area
12
.
Word lines of a multi-bank structure are required to traverse only the bit line pairs confined within one bank, instead of the entire bit line pairs within the chip
1
. Therefore, the length and capacitance of the word lines are significantly reduced. Also, the memory array blocks
10
are not only divided in the column direction (left and right memory array blocks) but also the row direction (eight banks in each memory array block
10
), and the number, length and capacitance of the word lines and bit lines in each bank is thus also reduced.
Another goal of a modem DRAM design is to increase the device density as much as possible. It is conventionally possible to design a memory chip with a high array efficiency so that the area ratio between the area occupied by the memory cells and the total chip space is in the range between 55% to 70%. The “high-density” devices, however, suffer speed penalty because of the heavy loading of word lines and bit lines.
In a micro-cell design, the loading of word lines can be reduced to about one sixteenth of that of the conventional word lines, and the loading of bit lines can be reduced to about one fourth of that of the conventional bit lines, by reducing the memory array size. Therefore, the access time and cycle time of the micro-cell type DRAM can be as short as 3 nanoseconds to 6 nanoseconds with a cycle time potentially as short as 10 nanoseconds while the access time of the word line and bit line of the high-density devices are from 10 nanoseconds to 30 nanoseconds. However, to further divide the array to reduce the word line length and number as described above, the array efficiency of the micro-cell DRAM is less satisfactory as compared to the high-density devices, and is in the range of 45% to 55%.
To improve the array efficiency of the micro-cell architecture, a “stacked-bank architecture” has been proposed, in which at least one bank is stacked on the top of another bank.
FIG. 2
depicts a multi-bank semiconductor memory device
1
having a plurality of banks
14
arranged in a multi-bank structure, in which bank
1
, bank
2
, bank
9
and bank
10
are stacked on bank
3
, bank
4
, bank
11
and bank
12
, respectively. Also, bank
5
, bank
6
, bank
13
and bank
14
are stacked on bank
7
, bank
8
, bank
15
and bank
16
, respectively. In other words, in a stacked-bank structure, one bank (i.e., bank
3
) is arranged between another bank (i.e., bank
1
) and the spine area
12
which includes a global address bus and data bus.
However, in general, a stacked-bank architecture has been avoided because of difficulty in designing a decoding scheme. Particularly, since one bank (e.g., bank
1
) is blocked from the spine area
12
by another bank (e.g., bank
3
), it has not been possible to access both of the stacked banks (e.g., bank
1
and bank
3
) simultaneously for different operations. For example, when memory cell addresses transferred from the main memory bus indicates a read operation in bank
1
and a write operation in bank
3
, first a bank address for the read operation is transferred to both bank
1
and bank
3
. Based on the bank address, bank
1
is activated for the read operation while bank
3
is not activated until bank
1
completes the read operation. Upon completing the read operation in bank
1
, another bank address for the write operation is transferred to both of bank
1
and bank
3
. The matching bank
3
is then activated for the write operation while bank
1
is not activated. Thus, although a stacked-bank architecture provides an improved array efficiency and cycle time, due to the difficulty in designing an efficient decoding scheme, a stacked-bank architecture has not provided flexibility of operation in a single cycle, and the full potential response speed has not been achieved.
On the contrary, application of a micro-cell design to larger memories results in the number of banks (i.e., 1024 banks) being dra

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