Decoding packets with deadlines in communications channels...

Details Decoding packets with deadlines in communications channels... Decoding packets with deadlines in communications channels...

2011-08-30

2011-08-30

Phillips, Hassan (Department: 2467)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S229000, C370S230000, C370S352000, C370S389000, C370S392000, C370S394000

Reexamination Certificate

active

08009688

ABSTRACT:
A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.

REFERENCES:
patent: 6014690 (2000-01-01), VanDoren et al.
patent: 6373842 (2002-04-01), Coverdale et al.

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