Decoding circuit for controlling activation of wordlines in...

Details Decoding circuit for controlling activation of wordlines in... Decoding circuit for controlling activation of wordlines in...

2001-06-05

2002-12-03

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S203000, C365S233100, C365S201000

Reexamination Certificate

active

06490222

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Cross-References to Related Applications
This application relies for priority upon Korean Patent Application No. 2000-39993, filed on Jul. 12, 2000, the contents of which are herein incorporated by reference in their entirety.
2. Field of the Invention
The present invention is in the field of a semiconductor memory device and is more specifically related to a decoding circuit for controlling activation of wordlines in a semiconductor memory device for a test function.
3. Description of the Prior Art
A high-density memory such a dynamic random access memory (RAM) has various test operation modes for verifying reliability thereof. The tests are carried out with various conditions and circumstance before and after completing a fabricating process. One of the test functions applied on a dynamic RAM is a burn-in test where stress of high voltage impacts on memory cells thereof and then primary defects such as micro-bridges are detected. The micro-bridges are induced from undesired short circuit phenomenon due to particles or impurities making electrically conductive paths between lines (e.g., wordlines or bitlines) which should not form a short circuit or a direct interconnection.
FIGS. 1A and 1B
show wordline activation patterns to find out micro-bridges over a memory cell array of a dynamic RAM. Referring to
FIG. 1A
, for screening micro bridges, data “
1
” is written in all memory cells, and then data “
0
” is written in memory cells coupled to one wordline. Thereafter, the wordline coupled to the memory cells storing the data “
0
” is activated for a time and set on a test voltage (i.e., high voltage for stress). If there is a micro-bridge between the memory cells storing “
0
” and “
1
”, the data of the memory cells which has stored data “
1
” is changed to “
0
”, which indicates that there is a micro-bridge between the bitlines of the memory cells.
It is known to activate a wordline at intervals of four wordlines, as shown in FIG.
1
B. This method results in a reduced test time for micro-bridges to one-fourth that of FIG.
1
A. If, for example, the number of wordlines in a unit array block is 512, then the active pattern of wordlines for the flow of the test operation are wordlines WL
0
, WL
4
, . . . , WL
508
. These wordlines, activated until the end of a stress time (step S
24
-
FIG. 3
) and coupled to memory cells storing data “
0
”, are all turned off at the same time. Since this method results in a number of the wordlines (i.e., 128 wordlines per the unit array block) being set to a low level (e.g. ground voltage) from high level, bouncing noises at the ground level (or ground noises) are induced thereby causing an increase of the ground voltage level that makes the low level be instantly higher. As a result, the data “
1
” stored in the memory cells coupled to the deactivated wordlines are undesirably changed into “
0
” because charges in the 1-storing memory cells are flow out from their bitlines.
SUMMARY OF THE INVENTION
The present invention is intended to solve these problems. It is an object of the invention to provide a decoding circuit capable of reducing ground noises in a test operation mode.
It is another object of the invention to provide a decoding circuit capable of performing a reliable test operation without an invalid disturbance.
It is yet another object of the invention to provide a method for testing the presence of micro-bridges without ground noises.
In order to accomplish those objects, a semiconductor memory device of the invention includes: main decoders for generating wordline enable signals in response to first decoding signals, a first precharge signal, and a second precharge signal; wordline drivers for wordline drive signals in response to the wordline enable signals and second decoding signals; and a circuit for generating the second precharge signal in response to a command signal. The wordline drive signals are inactivated in sequence in response to the first decoding signals and the second precharge signal, in order to reducing ground noises.


REFERENCES:
patent: 5047983 (1991-09-01), Iwai et al.
patent: 5373471 (1994-12-01), Saeki et al.
patent: 5631871 (1997-05-01), Park et al.
patent: 5798973 (1998-08-01), Isa
patent: 5864508 (1999-01-01), Takashima et al.
patent: 6055206 (2000-04-01), Tanizaki et al.
patent: 6088286 (2000-07-01), Yamauchi et al.

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