Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding
Patent
1996-04-23
1999-11-02
Tokar, Michael
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Decoding
36523006, H03K 19084
Patent
active
059777990
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a storing circuit for use with a semiconductor storing apparatus, in particular, a non-volatile memory such as a mask ROM (Read Only Memory) with a large storage capacity.
RELATED ART
A conventional non-volatile memory has an X decoder that drives a word line corresponding to a memory cell. The X decoder has a P channel type field effect transistor (hereinafter referred to as PMOS) and an N channel type field effect transistor (hereinafter referred to as NMOS) that are connected between a power voltage and a node. A connected portion of the PMOS and the NMOS is connected to the word line.
However, as the storage capacity of the mask ROM increases, the gate length of the NMOS of the X decoder tends to decrease.
Thus, in the standby state, if the voltage of the word line is high (hereinafter, this state is referred to as H level) and the voltage of the node is low (hereinafter, this state is referred to as L level), a leak current may flow in the PMOS due to the short channel effect.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a storing circuit for use with a semiconductor apparatus that can prevent a leak current from flowing in standby state and to decrease power consumption.
A first aspect of the present invention is a storing circuit for use with a semiconductor apparatus, comprising a first-conductor type first transistor connected between a constant voltage node and a first node, a second-conductor type second transistor connected between the first node and a first node, the polarity of the second-conductor type second transistor being reverse of the polarity of the first-conductor type first transistor, a word line connected to the first node, a first logic circuit with a plurality of input portions and an output portion, the output portion being connected to the second node, the first logic circuit being adapted for supplying a second voltage to the second node in the case that at least one of signals supplied to the input portions is in a first voltage level, and a second logic circuit with two input portions and two output portions, one of the output portions being connected to one of the input portions of the first logic circuit, the second logic circuit being adapted for outputting output signals corresponding to a chip enable signal, outputting signals that are in a first voltage level from the two output portions in the case that the voltage level of the chip enable signal is the first voltage level, and outputting signals that are in levels complementary each other from the two output portions when the voltage level of the chip enable signal is the second voltage level.
According to the first aspect of the present invention, the first logic circuit is for example composed of a predecoder element circuit shown in FIG. 1 (ii), a NAND gate 19, and inverters 20 and 21 shown in FIG. 1 (iii).
According to the first aspect of the present invention, the second logic circuit is composed of an address buffer element circuit shown in FIG. 1 (i).
A second aspect of the present invention is a storing circuit for use with a semiconductor apparatus, comprising a first-conductor type first transistor connected between a constant voltage node and a first node, a second-conductor type second transistor connected between the first node and a second node, the polarity of the second-conductor type second transistor being reverse of the polarity of the first-conductor type first transistor, a word line connected to the first node, a logic circuit connected to the second node and having a plurality of input portions for inputting a plurality of address signals or inverted signals thereof and a inverted signal of a chip enable signal, the logic circuit being adapted for supplying a second voltage to the second node regardless of the voltage levels of the address signals or the inverted signals thereof in the case that the voltage level of the inverted signal of the chip enable signal is a second voltage level and for supplying to th
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Richard D. Jolly et al. A 35-ns 64K EEPROM. IEEE Journal of Solid-State Circuits, vol. 20, No. 5, Oct. 1985, New York, USA. pp. 971-978. p. 973, left-hand column line 3--p. 974, left-hand column, line 11; figures 3, 4.
Kai Nobuhiro
Kokubun Hitoshi
Frank Robert J.
OKI Electric Industry Co., Ltd.
Roseen Richard
Sartori Michael A.
Tokar Michael
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