Decoding apparatus, trellis processor, and method for...

Details Decoding apparatus, trellis processor, and method for... Decoding apparatus, trellis processor, and method for...

2007-09-11

2007-09-11

Dildine, R. Stephen (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S792000, C714S794000, C714S795000

Reexamination Certificate

active

10799099

ABSTRACT:
A decoding apparatus includes at least one decoder both for a turbo-decoding and for a Viterbi decoding, at least one first data path for the Viterbi decoding of a convolution code, at least one second data path for the decoding of a turbo code, and a common memory having a multiplicity of individual memory areas. It is possible to allocate at least one memory area both through the first data path in the Viterbi mode and through the second data path in the turbo mode. The invention also includes a trellis processor and a method for operating a decoding apparatus in which at least parts of the first data path and of the second data path can be utilized jointly both for the turbo decoding and for the Viterbi decoding.

REFERENCES:
patent: 2002/0015401 (2002-02-01), Subramanian et al.
patent: 2002/0119803 (2002-08-01), Bitterlich et al.
patent: 2003/0026359 (2003-02-01), Loeliger et al.
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patent: 2004/0174848 (2004-09-01), Takayama et al.
patent: 2004/0243908 (2004-12-01), Box et al.
patent: 2006/0003795 (2006-01-01), Yamanaka et al.
patent: 0 653 847 (1995-05-01), None
patent: 02/21699 (2002-03-01), None

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