Decoding apparatus, decoding method, and program to decode...

Details Decoding apparatus, decoding method, and program to decode... Decoding apparatus, decoding method, and program to decode...

2007-11-20

2007-11-20

Lamarre, Guy (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

Reexamination Certificate

active

10521054

ABSTRACT:
The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P×P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P×P) 0-matrix. A check node calculator313simultaneously performs p check node calculations. A variable node calculator319simultaneously performs p variable node calculations.

REFERENCES:
patent: 6539367 (2003-03-01), Blanksby et al.
patent: 6633856 (2003-10-01), Richardson et al.
patent: 6785863 (2004-08-01), Blankenship et al.
patent: 6938196 (2005-08-01), Richardson et al.
patent: 6957375 (2005-10-01), Richardson
patent: 6961888 (2005-11-01), Jin et al.
patent: 2002/0186759 (2002-12-01), Goldstein et al.
patent: 2004/0019845 (2004-01-01), Eroz et al.
patent: 2004/0034828 (2004-02-01), Hocevar
patent: 2004/0187129 (2004-09-01), Richardson
patent: 2005/0278606 (2005-12-01), Richardson
patent: 1 158 682 (2001-11-01), None
patent: 2002-33670 (2002-01-01), None
patent: 2003-269302 (2003-09-01), None
Robert G. Gallager,Low-Density Parity Check Codes(M. I. T. Press 1963).
David J. C. MacKay, “Good Error-Correcting Codes Based on Very Sparse Matrices,”IEEE Transactions on Information Theory, vol. 45, No. 2, pp. 399-431, Mar. 1999.
Michael G. Luby, Michael Mitzenmacher, M. Amin Shokrollahi & Daniel A. Spielman, “Analysis of Low Density Codes and Improved Design Using Irregular Graphs,”Proceedings of ACM Symposium on Theory of Computing, pp. 249-258 (1998).
C. Howland & A. Blanksby, “Parallel Decoding Architectures for Low Density Parity Check Codes,”Symposium on Circuits and Systems, part IV, pp. 742-745 (2001).
Engling Yeo, Payam Pakzad, Borivoje Nikolic & Venkat Anantharam, “VLSI Architectures for Iterative Decoders in Magnetic Recording Channels,”IEEE Transactions on Magnetics, vol. 37, No. 2, pp. 748-755, Mar. 2001.
S. Kim et al, ‘Parallel VSLI Architectures for a Class of LD PC Codes’, IEEE International Symposium on Circuits and Systems, 2002, ISCAS 2002, vol. 2, Nov. 2002, p. 26-29.

Affiliated with

Also associated with

Rating

Decoding apparatus, decoding method, and program to decode... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Decoding apparatus, decoding method, and program to decode..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Decoding apparatus, decoding method, and program to decode... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3864475