Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-04-20
2011-12-27
Alphonse, Fritz (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S752000, C714S780000
Reexamination Certificate
active
08086934
ABSTRACT:
A decoding apparatus and method are capable of decoding LDPC codes with a high degree of precision while preventing the circuit scale of the decoding apparatus from increasing. A computation section carries out a first computation process corresponding to three check-node processes by making use of decoding intermediate results supplied from a decoding intermediate result storage memory by way of a cyclic shift circuit, and stores the result of the first computation process in a decoding intermediate result storage memory. A computation section carries out a second computation process corresponding to six variable-node processes by making use of decoding intermediate results supplied from a decoding intermediate result storage memory by way of a cyclic shift circuit, and stores the decoding intermediate result in the decoding intermediate result storage memory.
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Japanese Office Action for Japanese Patent Application No. 2005-125962 dated Jul. 15, 2010.
Miyauchi Toshiyuki
Shinya Osamu
Yokokawa Takashi
Alphonse Fritz
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Sony Corporation
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