Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding
Reexamination Certificate
2001-02-20
2002-09-24
Le, Don Phu (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Decoding
C326S083000, C326S089000
Reexamination Certificate
active
06456119
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a decoding apparatus for transmitting a high voltage signal.
In the fields of microelectronics, information technology, and the like, it is often necessary to code and/or decode a multiplicity of addresses for electronic components in hardware. Such coding/decoding is performed in order to address memory elements, sensor elements, e.g., in image sensors, actuator elements, or the like, and, consequently, to call up their contents in order to read them, change their state, or the like.
In particular, in the case of memory chips, such as DRAMs, it is customary to select individual word lines from predecoded addresses in a word line decoder. In such a context, in prior art decoding apparatuses, in particular, for transmitting high voltage signals, a final decoder is provided for the switchable transmission of a transmission signal. In addition, a transmission signal line device is configured to supply the transmission signal to the final decoder, and a driver signal line device is configured to supply a driver signal to the final decoder. Also, an output signal line device is configured to output an output signal from the final decoder. The final decoder has a first switching device, with at least one field effect transistor as the switching element. In these prior art decoding apparatuses, the gate line of the respective field effect transistor can have the driver signal applied to it, and the respective source line can have the transmission signal applied to it, specifically such that, when the driver signal is reset—e.g., from high to low, the output signal can be connected to the output signal line device and appears there.
Thus, the effect achieved in the prior art decoding apparatus is that a high voltage output signal appears at the output of the final decoder if the corresponding driver signal on the gate line changes from high to low.
There is a disadvantageous aspect of the construction of these prior art decoding apparatuses, particularly when high voltage signals are being transmitted, because particular circumstances do not allow the temporal relationship, that is to say, in particular, the time interval, between the high/low change of the driver signal and the low/high change of the transmission signal to be observed. Such observation is not allowed because, if the driver signal changes to low while the output signal is already rising or has already risen, the output characteristic curve of the appropriate field effect transistor would be traversed from the saturation region to the resistance region, that is to say under load. In such a context, however, high channel voltages in the transmission channel may arise in the saturation region, and, consequently, there is a high likelihood that the line channel of the transistor will be degraded. The channel degradation is based to a considerable extent on the fact that hot electrons at the semiconductor/insulator interface, in particular, the Si/SiO
2
interface, cause faults. These faults can result in the threshold voltage being shifted and in the channel mobility being reduced. Degradation of the transistor and its consequential phenomena increase the likelihood of a permanent change in the transistor properties and in its switching response, and the likelihood of failure also increases. Hence, there is also the possibility of damage to the component, to the memory chip, or the like.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a decoding apparatus that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type and in which the likelihood of damage and of failure when high voltage signals are being transmitted is particularly small.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a decoding apparatus for transmitting a high voltage signal, including a final decoder for switchably transmitting a transmission signal, the final decoder having a switching device, a transmission signal line device configured to supply the transmission signal to the final decoder, a driver signal line device configured to supply a driver signal to the final decoder, and an output signal line device configured to output an output signal from the final decoder, the switching device having at least one field effect transistor with a gate line, a source line, and an output, the at least one field effect transistor having a low threshold voltage, the driver signal line device connected to the gate line for applying the driver signal to the gate line, the transmission signal line device connected to the source line for applying the transmission signal to the source line, the output signal line device selectively connected to the output, and the at least one field effect transistor configured to selectively connect the output signal to the output signal line device through the output in response to a reset of the driver signal.
The first way in which the invention achieves its objectives is for the field effect transistor in the first switching device of the final decoder to be respectively constructed to have a low threshold voltage, to wit, between 0.1 and 0.4 volts. The effect achieved by the low threshold voltage is that, when the driver signal changes from high to low, the field effect transistor is actually taken as early as possible, i.e., without any load, from the saturation region into the resistance region, so that the smallest possible time overlap between the high/low change in the driver signal and the low/high change in the transmission signal results. Therefore, the likelihood of channel degradation is reduced.
In such a case, it is particularly advantageous that the respective field effect transistor in the first switching device of the final decoder is a low VT field effect transistor.
With the objects of the invention in view, there is also provided a decoding apparatus for transmitting a high voltage signal, including a final decoder for switchably transmitting a transmission signal, the final decoder having a switching device, a transmission signal line device configured to supply the transmission signal to the final decoder, a driver signal line device configured to supply a driver signal to the final decoder, and an output signal line device configured to output an output signal from the final decoder, the switching device having at least one depletion-mode-type field effect transistor with a gate line, a source line, and an output, the driver signal line device connected to the gate line for applying the driver signal to the gate line, the transmission signal line device connected to the source line for applying the transmission signal to the source line, the output signal line device selectively connected to the output, and the at least one field effect transistor configured to selectively connect the output signal to the output signal line device through the output in response to a reset of the driver signal.
In accordance with a further way in which the invention achieves the object, provision is made for the field effect transistor in the first switching device of the final decoder to be respectively a depletion mode field effect transistor, in particular, a depletion mode PFET. The configuration likewise increases the likelihood that, in the event of a time overlap between a falling driver signal and a rising transmission signal, the transistor operates in the resistance region, and, therefore, outside the saturation region, at an earlier instant. As a result, the time overlap and, hence, the likelihood of channel degradation are reduced. Preferably, the depletion mode type field effect transistor has a low threshold voltage, preferably, between 0.1 and 0.4 volts. In particular, the depletion mode field effect transistor is a normally-on, depletion mode field effect transistor.
It can be regarded as a further advantage that the field effect transistor in the first switching device of the final decoder is respective
Greenberg Laurence A.
Infineon - Technologies AG
Le Don Phu
Mayback Gregory L.
Stemer Werner H.
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