Decoder with reduced architecture

Details Decoder with reduced architecture Decoder with reduced architecture

1995-11-17

1998-04-21

Westin, Edward P.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

326108, 326121, H03K 19084, H03K 1920

Patent

active

057421870

ABSTRACT:
An improved decoder with a reduced architecture that decodes a plurality of input signals that include a least significant input signal. The decoder comprises at least one pair of adjacent logic gates, each of the at least one pair of logic gates receiving at least one logic input signal that is selected from a group of logic signals that include the input signals to the decoder and the inverse of the input signals to the decoder. The logic input signals received by the at least one pair of adjacent logic gates are common to both adjacent logic gates of the pair, except for those logic signals representing the least significant decoder input signal and the inverse of the least significant decoder signal.

REFERENCES:
patent: 3439185 (1969-04-01), Gibson
patent: 3539823 (1970-11-01), Zuk
patent: 3851186 (1974-11-01), Koo
patent: 3904888 (1975-09-01), Griffin et al.
patent: 4866305 (1989-09-01), Hasegawa
patent: 5309043 (1994-05-01), Murahashi

Affiliated with

Also associated with

Rating

Decoder with reduced architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Decoder with reduced architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Decoder with reduced architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2061461