Decoder testing apparatus and methods that simultaneously...

Details Decoder testing apparatus and methods that simultaneously... Decoder testing apparatus and methods that simultaneously...

1998-06-23

2002-05-07

Brier, Jeffery (Department: 2672)

Coded data generation or conversion

Converter calibration or testing

C345S904000, C702S118000, C324S701000

Reexamination Certificate

active

06384754

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to decoders such as are used to drive the pixels of a display, and more particularly to testing of decoders.
BACKGROUND OF THE INVENTION
Decoders are widely used in displays, such as Liquid Crystal Displays (LCDs). As is well known to those having skill in the art, in an LCD, a source driver for a thin film transistor (TFT) drives the thin film transistor with an output voltage that corresponds to data for displaying the brightness of the red (R), green (G) and blue (B) portions of a given pixel. In one example, 300 decoders may be present, each of which is responsive to one of 64 contrast levels, to produce a respective output level corresponding to the selected contrast level. The 64 contrast levels may be provided using six bits of multibit input data, to provide a selected voltage V
1
-V
64
corresponding to 64 output levels.
In view of the large numbers of decoders and the large numbers of output levels that each decoder can provide, testing of the decoders may be extremely time consuming. More specifically, in conventional test programs, the output of each decoder is cycled through each of the output levels. Thus, if 300 decoders are present, each of which provides an output voltage level V
1
-V
64
in response to six bits of input data, 65 cycles may be needed to test all of the output voltage levels. Each cycle may use at least 100 shift clocks and one latch clock. Accordingly, the time for testing the decoders can be unacceptably long.
FIGS.
1
(
a
)-
1
(
f
) are conventional timing diagrams for conventional decoder testing. Input data for a plurality of channels is serially latched into a data register in response to a shift clock (SCLK) shown in FIG.
1
(
a
). All the data latched to the data register is simultaneously output in response to a latch clock (LCLK) shown in FIG.
1
(
b
). A conventional test for decoders may use 100 shift clocks since input data with respect to R, G and B are input at one time in response to one clock of the shift clock (SCLK).
FIG.
1
(
c
) shows input data which has the same value. Real input data is separate data; however, data having the same value are used for a test. FIGS.
1
(
d
) through
1
(
f
) show the outputs of output channels OUT
1
through OUT
300
, which are output at one time in response to the latch clock (LCLK). As shown, times of 64 contrast levels×100 shift clocks may be needed if such outputs are performed with respect to 64 contrast levels.
As a result, a testing time of at least the number of contrast levels times the period of shift clock times the number of outputs may be needed for testing the decoders. Since more than five types of tests may be performed in order to test a decoder in an integrated circuit, most of the test time for the integrated circuit may be consumed on testing the decoders.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide improved decoders and decoder testing methods.
It is another object of the present invention to provide decoders and decoder testing methods that can reduce the amount of time that is used to test the decoders.
These and other objects are provided according to the present invention, by simultaneously applying the same multibit input data to a plurality of decoders in response to a test mode signal. It has been found, according to the invention, that since all of the decoders are being tested, the same data may be input to all of the decoders without inputting separate data through the decoder input terminals, as is the case during normal decoding operations. Accordingly, the time for testing the decoders can be reduced.
More specifically, according to the invention, a decoding system includes a plurality of decoders, a respective one of which is responsive to respective multibit input data, to decode the respective multibit input data and produce a respective output level corresponding to the respective multibit input data. Means and methods are provided for simultaneously applying the same multibit input data to the plurality of decoders, in response to a test mode signal. Different multibit input data is then simultaneously applied to the plurality of decoders, so that all of the output levels of the decoders can be tested. The output levels from the plurality of decoders that result from the same multibit input data that is supplied to the plurality of decoders is detected. The detected output levels from the plurality of decoders that result from the same multibit input data that is applied to the plurality of decoders is compared to expected output levels in order to test the decoders. The multibit input data preferably is N-bit input data, so that one of 2
N
combinations of the N-bits is simultaneously applied to the plurality of decoders in response to the test mode signal.
In a preferred embodiment, the plurality of decoders comprises a plurality of red, green and blue signal decoders for a color display. The same first multibit input data is simultaneously applied to the plurality of red decoders, the same second multibit input data is simultaneously applied to the plurality of green decoders, and the same third multibit input data is simultaneously applied to the plurality of blue decoders, in response to the test mode signal.
The same multibit input data is preferably simultaneously applied to the plurality of decoders by providing a plurality of data registers that latch the same multibit input data therein and that simultaneously apply the latched multibit input data to the plurality of decoders. A controller produces a shift clock and a latch clock in response to the test mode signal. A shift register is responsive to the shift clock to generate a plurality of input control clocks. The plurality of data registers are responsive to the plurality of input control clocks, to latch the same multibit input data therein. The data registers are responsive to the latch clock, to simultaneously apply the latched multibit input data to the plurality of decoders.
Accordingly, improved decoders and testing apparatus and methods for decoders are provided that can reduce the testing time for the decoders.


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Wiley Encyclopedia of Electrical and Electronics Engineering, J. G. Webster, 1999, Wiley, vol. 5, p. 518-519.

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