Decoder for saving power consumption in semiconductor device

Details Decoder for saving power consumption in semiconductor device Decoder for saving power consumption in semiconductor device

1997-12-30

2001-05-01

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C326S093000

Reexamination Certificate

active

06225828

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a decoder using a BiCMOS inverter in a semiconductor and, more particularly, to a decoder capable of saving power consumption.
2. Description of the Related Art
In general, a BiCMOS circuit operates at a high speed, by combining the high driving force of a bipolar transistor and the stable operation characteristics of CMOS transistors. A conventional inverter using BiCMOS transistors doesn't operate with a full swing width which is in a voltage level of the CMOS transistor based on the characteristics of bipolar transistor. The voltage swing of a BiCMOS inverter is decreased by Vbe (base to emitter) voltage, 0.8V. That is, the high voltage level is Vcc to 0.8V and the low voltage level is 0V.
Accordingly, in case where this BiCMOS circuit is used, it is essential that CMOS transistors in a CMOS inverter in the next stage may consume current in their operations. Since the voltage drop of 0.8V is sufficient to weakly turn on a PMOS transistor to be turned off, a CMOS inverter formed between a power supply and a ground voltage level, which includes the PMOS transistor coupled in series to an NMOS transistor, may consume a large amount of current, in particular, in a stand-by state.
To decrease this current consumption, transistors to compensate the voltage drop are added to the inverter for the full swing in the CMOS voltage level. However, this additional transistor increases the area of layout.
FIG. 1
is a schematic view illustrating a conventional BiCMOS inverter. As shown in
FIG. 1
, the conventional BiCMOS inverter includes a PMOS transistor
101
, NMOS transistors
114
and
115
and a bipolar transistor
122
. The PMOS transistor
101
has a gate coupled to an input terminal of the inverter and transfers a voltage from a power supply to a base of a bipolar transistor
122
. The NMOS transistor
114
, which is coupled in series to the PMOS transistor
101
, has a gate coupled to the input terminal of the inverter and a source coupled to a ground voltage level. The bipolar transistor
122
has a collector coupled to the power supply and an emitter coupled to an output terminal of the inverter. The NMOS transistor
115
has a gate coupled to the input terminal of the inverter, a drain coupled to the emitter of the bipolar transistor
122
and a source coupled to a ground voltage level.
In case where the transition in going from a high voltage level to a low voltage level is achieved, the current flowing the PMOS transistor
101
applies a voltage to the base of the bipolar transistor
122
so that the output terminal of the inverter becomes a high voltage level. The minimum voltage for turning on the bipolar transistor
122
, vbe, is approximately 0.7 to 0.8V. When the voltage of the output terminal increases up to Vcc-Vbe, the voltage difference between the base and the emitter of the bipolar transistor
122
is Vbe. Accordingly, since the bipolar transistor
122
is turned off when the output voltage increases over Vcc-Vbe, the maximum voltage of the output terminal may be Vcc-Vbe. If the output voltage of the inverter drives a CMOS inverter in the next stage, an input voltage applied to the CMOS inverter is Vcc-Vbe. This input voltage makes a direct current path from the power supply to the ground voltage level in the next stage, by simultaneously turning on the PMOS and NMOS transistors in the CMOS inventer. As a result, the inverter having this current path cannot be used in a low power devices.
On the other hand, in case where the transition in going from a low voltage level to a high voltage level is achieved in a voltage applied to the input terminal, the NMOS transistor
114
is turned on so that the base of the bipolar transistor
122
is in a ground voltage level and the NMOS transistors
114
and
115
acts as pull-down transistors which make the output of the inverter low.
The circuit as shown in
FIG. 1
is an example of BiCMOS inverter but different inverters can be used for other purposes. However, these inverters may consume a large amount of current when the stand-by state is a high voltage level. Also, an addition of transistors operating in the CMOS level increases the area of the layout.
FIG. 2
is a schematic view illustrating an example of conventional decoder using the BiCMOS inverter of FIG.
1
. The conventional decoder receives addresses from “n” input terminals and then outputs values of “1” or “0” to “2
n
” output terminals.
The conventional decoder, as shown in
FIG. 2
, includes four NAND gates
205
having two input terminals and four inverters
210
. The two-input NAND gates
205
receives two of input signals A
0
, A
1
, A
0
B and A
1
B. The inverters
210
receives the outputs from the NAND gates
205
and then outputs decoded output signals D
0
, D
1
, D
2
and D
3
, respectively. Also, only one of the output signals D
0
, D
1
, D
2
and D
3
may be in a high voltage level and the decoder typically employs a latch circuit to temporally store an output data in a storage circuit for the next cycle.
Referring to
FIG. 3
showing a timing diagram of
FIG. 2
, when the transition of input signals A
0
and A
1
is achieved form a low voltage level to a high voltage level
312
in cycle
0
, the output signal D
3
rises to a high voltage level
316
and the output signal D
0
achieves the transition from a high voltage level
326
to a low voltage level
328
. At this time, the high voltage levels
316
and
326
are in the voltage of Vcc-Vbe and the low voltage levels
318
and
328
are the ground voltage level. One of the outputs D
0
to D
3
of the decoder is always in a high voltage level so that the power consumption occurs. In particular, this power consumption may always occur in the stand-by state.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a decoder using a BiCMOS inverter and being capable of reducing power consumption without a chip area increase which is caused by the modification of an inverter.
In accordance with an aspect of the present invention, there is provided a decoder in a semiconductor device comprising: a plurality of NAND gates receiving addresses; a plurality of BiCMOS inverters for inverting outputs from the NAND gates; a clock generator for providing a clock signal for the NAND gates, whereby the clock signal controls outputs from the BiCMOS inverters. The BiCMOS inverters are respectively coupled to CMOS inverters and disabled when the clock signal is in a low voltage level. The clock signal is in a low voltage level when the decoder is in a stand-by state.


REFERENCES:
patent: 4837462 (1989-06-01), Watanabe et al.
patent: 5097158 (1992-03-01), Michel
patent: 5103113 (1992-04-01), Inui et al.
patent: 5894231 (1999-04-01), Kuhara
Rhyne, Fundamentals of Digital Systems Design, N.J., pp.70-71, 1973.*
Rudolf F. Graf, Modern Dictionary of Electronics, Howard W. Sams & Co., Inc, pp.165, 1984.

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