Decoder for memory device

Details Decoder for memory device Decoder for memory device

2006-10-24

2006-10-24

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S230060, C365S149000, C365S185230, C327S106000

Reexamination Certificate

active

07126862

ABSTRACT:
A decoder for a memory device includes driving devices each applying a respective line voltage to a respective line of the memory device when turned on. The decoder also includes a control device coupled to the plurality of driving devices at a common node for generating a voltage that controls the driving devices to turn on or off. Also, a capacitor coupled to the common node increases the voltage at the common node from an initial boost voltage to a final boost voltage. Thus, a line of a memory device is driven to a boost voltage with minimized area and wiring complexity.

REFERENCES:
patent: 4455629 (1984-06-01), Suzuki et al.
patent: 5404329 (1995-04-01), Yamagata et al.
patent: 5467032 (1995-11-01), Lee
patent: 5923596 (1999-07-01), Wu et al.
patent: 6085800 (2000-07-01), Usui
patent: 6137733 (2000-10-01), Watanabe
patent: 6421295 (2002-07-01), Mao et al.
patent: 6535430 (2003-03-01), Ogura et al.
patent: 6646950 (2003-11-01), Akaogi

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