Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding
Reexamination Certificate
1999-06-18
2001-01-09
Nelms, David (Department: 2818)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Decoding
C365S203000
Reexamination Certificate
active
06172530
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a decoder arranged to generate N output signals from two or more precharged input signals.
2. Description of the Prior Art
It is often necessary to provide decoder circuits for producing a number of output signals based on two or more precharged input signals. The output signals generated by the decoder circuit may, for example, be used as input signals to domino logic. During the precharge phase, it is typically required that all of the output signals from the decoder are at the same logic value, and that during the subsequent evaluate phase, one of the output signals transitions to another logic value. For example, if a decoder circuit is to produce outputs suitable for use with a CMOS domino logic wired NOR gate, then the required behaviour is that during the precharge phase all of the outputs of the decoder are at a logic 0 level, and that during the subsequent evaluate phase exactly one output makes a single transition from a logic zero to a logic 1 value. It is also necessary to ensure that all of the output signals from the decoder circuit are valid after the single transition of one of the outputs has taken place.
For decoder circuits using precharged inputs, the above behaviour is that of a decoder implemented using an AND gate structure to produce the outputs. Considering the example of an N bit encoded input, this requires an N-input AND gate per output. An N-input AND gate requires either an N stack of n-type transistors, or an equivalent cascade of AND gates in series. However, as the number of inputs increases, an AND based decoder circuit becomes slower with the increased number of stacked or cascaded devices.
Accordingly, it is an object of the present invention to provide an improved decoder which during the precharge phase produces all of the outputs at the same logic value, and during a subsequent evaluate phase causes one of the output signals to make a transition to another logic value, whilst ensuring that all of the output signals are valid once that output signal has transitioned.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a decoder for generating N output signals, the decoder comprising: a precharged gate structure arranged to receive two or more input signals and to generate N intermediate signals, in a precharge phase said precharged gate structure being arranged to output said N intermediate signals at a first logic value, and in an evaluate phase said precharged gate structure being arranged to maintain a first intermediate signal at said first logic value, and to cause all other intermediate signals to transition to a second logic value; self-timed logic for receiving the N intermediate signals, and for generating said N output signals, the self-timed logic being arranged, during said precharge phase, to generate said N output signals at said second logic value, and during the evaluate phase to cause a first output signal corresponding to said first intermediate signal to transition to said first logic value; said self-timed logic being arranged to generate each output signal from the corresponding intermediate signal as qualified by a predetermined other intermediate signal, such that the transition of said first output signal to said first logic value is delayed by a first predetermined time after the predetermined other intermediate signal has transitioned to said second logic value.
In accordance with the present invention, the decoder includes a precharged gate structure which in the precharge phase is arranged to output N intermediate signals at a first logic value, and in an evaluate phase is then arranged to maintain a first intermediate signal at the first logic value, and to cause all other intermediate signals to transition to a second logic value. It will be appreciated that the behaviour of these intermediate signals is not the behaviour that is ultimately required of the output signals of the decoder, but it has been found that by allowing the precharged gate structure to produce such intermediate signals, it is possible for a more efficient precharged gate structure to be used in the decoder than would otherwise be possible if the precharged gate structure were to directly produce the desired output signals.
For example, with reference to the earlier described prior art decoder based on AND gates, it is now possible for the precharged gate structure to be constructed using NOR gates rather than AND gates. This is beneficial for large structures since an alternative way of implementing an AND function is to use the fact that:
X AND Y==NOT (NOT X OR NOT Y)
this relationship being known as the De Morgans equation. An N input OR gate can be implemented as a precharged NOR gate, followed by an inverter. Accordingly, the above equation yields:
X AND Y==(NOT X) NOR (NOT Y)
The precharged NOR gate structure contains n-type transistors connected in parallel, and for large structures a precharged NOR gate is generally faster than a precharged AND gate.
However, with reference to the earlier discussions concerning the required behaviour for the decoder circuit, it is apparent that the outputs of a decoder circuit constructed using precharged NOR gates do not have the required behaviour for use with domino logic. Typically, for a precharged NOR gate structure, during the precharge phase, all of the outputs will be at a first logic value, and during the evaluation phase all but one output will make a transition from that first logic value to a second logic value. Hence, considering the earlier example, where the decoder circuit is to be used to provide input signals for a CMOS domino logic, at the start of the evaluation phase, all of the outputs will be at a logic 1 level, and during the evaluation stage, all but one output will make a single transition from logic 1 to logic 0.
However, in accordance with the present invention, the decoder also comprises self-timed logic which is arranged to manipulate the intermediate signals to produces the desired output signals, and also to ensure that all of the output signals are valid once one of the output signals has transitioned. Accordingly, the self-timed logic is arranged to receive the N intermediate signals, and during said precharge phase to generate N output signals at a second logic value. Then, during the evaluate phase, the self-timed logic is arranged to cause a first output signal corresponding to the first intermediate signal to transition to the first logic value. Further, the self-timing of the output signal is achieved by arranging the self-timed logic to generate each output signal from the corresponding intermediate signal as qualified by a predetermined other intermediate signal, such that the transition of the first output signal to the first logic value is delayed by a first predetermined time after the predetermined other intermediate signal has transitioned to the second logic value. By this approach, it is ensured that by the time the first output signal has transitioned to the first logic value, all of the other output signals will be valid.
In preferred embodiments, the self-timed logic comprises a logical AND gate for each intermediate signal, each logical AND gate being arranged to receive the corresponding intermediate signal and a second signal derived by inverting the predetermined other intermediate signal. Further, the self-timed logic preferably comprises an inverter associated with each AND gate, the inverter being arranged to receive at its input the predetermined other intermediate signal, and to generate at its output the second signal for inputting to the associated AND gate.
With the above preferred embodiment approach, it is possible to apply the delay in the transitioning of the first output signal to the first logic value by appropriate selection of the logic elements within the self-timed logic. More particularly, in preferred embodiments, the inverter is arranged to take said first predetermined time to generate the
Bull David Michael
Rose Andrew Christopher
ARM Limited
Nelms David
Nixon & Vanderhye P.C.
Tran M.
LandOfFree
Decoder for generating N output signals from two or more... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Decoder for generating N output signals from two or more..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Decoder for generating N output signals from two or more... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2554808