Decoder for executing error correction and error detection in pa

Details Decoder for executing error correction and error detection in pa Decoder for executing error correction and error detection in pa

1997-09-29

2000-09-12

De Cady, Albert

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

H03M 1300

Patent

active

061192600

ABSTRACT:
The present invention relates to an error correcting and detecting apparatus that executes a decode process at high speed. The error correcting and detecting apparatus receives digital data including an error correction code and an error detection code and performs error correction and error detection on the digital data. In one embodiment, the apparatus includes: an input interface for receiving the digital data from a recording medium and writing the digital data into a memory device; an error correction decoder for receiving the digital data from the memory device and performing error correction on the digital data in accordance with error correction codes; an error detection decoder for receiving the digital data from the memory device and performing error detection on the digital data in accordance with error detection codes; and an output interface for reading digital data from the memory device and outputting the read digital data, the read digital data having undergone the error correction and error detection. The error correction by the error correction decoder and the error detection by the error detection decoder are performed in parallel.

REFERENCES:
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patent: 5771248 (1998-06-01), Katayama et al.
Lee, patrick et al., Parallel Error-Trapping and Error-Detection Decoding, IEEE, pg. 35 to 38, Apr. 1991.

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