Decoder for executing a Viterbi algorithm

Details Decoder for executing a Viterbi algorithm Decoder for executing a Viterbi algorithm

2005-08-09

2009-11-03

Torres, Joseph D (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S794000, C714S796000

Reexamination Certificate

active

07613989

ABSTRACT:
A Viterbi decoder includes a computing device, a memory and a bus. The computing device receives sets of data values and calculates distances for the received sets of data values, accumulates and compares the calculated distances according to a Viterbi algorithm, decides data values and generates control signals dependent on a plurality of decisions associated with a plurality of paths. The memory stores the decided data values and provides at least one output value. The bus connects the computing device and the memory and is configured to convey the control signals to the path memory. The computing device or the memory shifts data strings in the memory according to conditions of the Viterbi algorithm with the control signals associated with the plurality of paths.

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