Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-05-24
2010-10-05
Baderman, Scott T (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07810010
ABSTRACT:
A Turbo Code decoder for implementation in an integrated circuit is described. An add-compare select (“ACS”) unit is configured to provide a difference between first and second outputs and to select one of the first and second outputs responsive to a difference thereof. An initialization stage is coupled to receive and configured to store for example the first output selected as an initialization value. A second select stage is coupled to receive for example the first output selected from the first select stage and coupled to obtain the initialization value stored from the initialization stage. The second select stage is configured to output either the first output selected from the ACS unit or the initialization value from the initialization stage.
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Xilinx, Inc., “3GPP Turbo Decoder”, DS318, Nov. 11, 2004, Product Specification, pp. 1-24, available from Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124.
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Ahmed Enam
Baderman Scott T
George Thomas
King John J.
Webostad W. Eric
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