Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2000-02-22
2001-03-20
Elms, Richard (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C257S776000
Reexamination Certificate
active
06205044
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a decoder connection configuration for memory chips having:
long bit lines running in a first direction;
word lines, which cross the bit lines in a memory cell array and run in a second direction;
word line decoders, which lie in a decoder region and form a first metallization plane, the decoder region adjoining an edge of the memory cell array that runs in the first direction; and
supply lines for the decoder, which are routed in the decoder region in a second metallization plane lying above the first metallization plane, respective plated-through holes being provided between the two metallization planes at lateral edges of the decoder region.
Array segments of integrated semiconductor memories and hence memory cell arrays are intended to be configured as large as possible in order to be able to store as much information as possible in each individual memory cell array. As contiguous array segments become larger, however, row decoders and/or row drivers also become longer, with the result that it becomes increasingly difficult to connect the decoders to power supply networks in a low-impedance manner.
At the present time, row decoders, as indicated in the introduction, are provided parallel to the bit lines at the edge of a memory cell array and, at the same time, are connected to a power supply network via plated-through holes in each case only at their ends. An existing configuration of this type is formed of memory cell array having word lines running in a y-direction and bit lines disposed in an x-direction. A decoder region is provided parallel to the bit lines at the edge of the memory cell array in the x-direction, in which decoder region the individual word lines and their decoders lie extremely close together. A row of power supply lines that are parallel to one another is provided in a second metallization plane above the decoders, which form a first metallization plane, in a manner insulated by a silicon dioxide layer. The power supply lines are electrically connected to the decoders only at the edge of the decoder region via plated-through holes running through the silicon dioxide layer. It is not possible for the plated-through holes to be provided in the course of the power supply lines, for instance in the center thereof, which is due to the fact that, in the metallization plane situated underneath, individual decoders and their word lines lie closely beside one another. Existing decoder connection configurations thus have the plated-through holes only at the edges of the decoder regions that adjoin the memory cell array.
It is a matter of great importance that the individual decoders be connected to the power supply lines with the lowest possible impedance, this currently being effected by the two-sided plated-through hole, at the two ends of the decoder region. Other possibilities consist in implementing the power supply lines as metal tracks that are as wide as possible, or in providing the decoders on both sides of the bit lines.
However, all these measures are associated with a higher area requirement, which is undesirable.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a decoder connection for memory chips with long BIT lines which overcomes the above-mentioned disadvantages of the prior art devices of this general type, in which a decoder connection can be connected with minimum impedance to power supply lines, without an additional area requirement in a memory cell array.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory chip, including:
a memory cell array having an edge and a bit line twist region;
long bit lines running in the memory cell array in a first direction and forming bit-line twists in the bit line twist region;
word lines crossing the long bit lines in the memory cell array and running in a second direction;
a decoder region adjoining the edge of the memory cell array and running in the first direction, the decoder region having lateral edges and a zone adjoining the bit line twist region;
word line decoders lying in the decoder region in a first metallization plane;
supply lines for the word line decoders, routed in the decoder region in a second metallization plane lying above the first metallization plane; and
a layer disposed between the first metallization plane and the second metallization plane and having plated-through holes formed therein running between the first metallization plane and the second metallization plane at the lateral edges of the decoder region, and additional plated-through holes formed in the layer running between the first metallization plane and the second metallization plane in the zone of the decoder region adjoining the bit line twist region.
The object is achieved according to the invention by virtue of the fact that in the memory cell array, the bit lines form a twist in a bit line twist region, and in that zone of the decoder region which adjoins the bit line twist region, additional plated-through holes are provided between the two metallization planes.
Thus, in the case of the decoder connection configuration according to the invention, unlike before, the two metallization planes are not connected to one another just at both ends of the decoder region, but rather at least one further time, for example in the center of the decoder region. For a realization of this additional connection of the two metallization planes which is neutral in terms of area, use is advantageously made of that zone of the decoder region which corresponds to the bit line twist region in the memory cell configuration.
In addition, by virtue of the bit line twist for the bit lines, the coupling capacitance thereof is practically halved on account of the twist, with the result that the bit lines can be configured to be longer than if there were no twists. In addition, it is possible to reduce the number of sense amplifiers on account of the smaller coupling capacitance, since practically every second sense amplifier can be omitted.
The invention thus makes it possible to reduce the power supply lines to approximately a quarter of their previous thickness or practically to double the length of the decoder region, without having to accept a reduction in the switching speed due to higher capacitances or RC constants.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a decoder connection for memory chips with long BIT lines, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 4977542 (1990-12-01), Matsuda et al.
patent: 5251168 (1993-10-01), Chung et al.
patent: 5534732 (1996-07-01), DeBrosse et al.
patent: 5625234 (1997-04-01), Suzuki et al.
patent: 5821592 (1998-10-01), Hoenigschmid et al.
patent: 5864496 (1999-01-01), Mueller et al.
patent: 6034879 (2000-03-01), Min et al.
patent: 6069815 (2000-05-01), Mueller et al.
Feurle Robert
Mandel Sabine
Schneider Helmut
Elms Richard
Greenberg Laurence A.
Infineon - Technologies AG
Lerner Herbert L.
Nguyen Hien
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