Decoder circuitry with balanced propagation delay and minimized

Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Decoding

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326 21, 326105, H03K 1920

Patent

active

053919416

ABSTRACT:
A logic circuit implementing a logic NAND function with respect to a first input signal and a second input signal is described. First and second P-channel transistors are coupled in parallel to a power supply and an output node. Each of the first and second P-channel transistors receives the respective one of the first and second input signals. A first circuit branch has a first and a second N-channel transistor. The first N-channel transistor has a first end coupled to the output node and a second end coupled to a first end of the second N-channel transistor. The second N-channel transistor has a second end coupled to ground. The first N-channel transistor receives the first input signal and the second N-channel transistor receives the second input signal. A second circuit branch has a third and a fourth N-channel transistor. The third N-channel transistor has a first end coupled to the output node and a second end coupled to a first end of the fourth N-channel transistor. The fourth N-channel transistor has a second end coupled to ground. The third N-channel transistor receives the second input signal and the fourth N-channel transistor receives the first input signal such that the logic circuit has a balanced propagation delay with respect to the first and second input signals. The logic circuit can be used to form a decoder circuit that has a balanced propagation delay for the input signals and a minimized input capacitance. The above described logic circuit can also be changed accordingly to implement a logic NOR function.

REFERENCES:
patent: 4433257 (1984-02-01), Kinoshita
patent: 4644189 (1987-02-01), Gabillard
patent: 5059825 (1991-10-01), Yoshida
patent: 5157283 (1992-10-01), Kin
patent: 5214606 (1993-05-01), Hashimoto

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