Decoder circuit which resists a fluctuation of a power supply

Details Decoder circuit which resists a fluctuation of a power supply Decoder circuit which resists a fluctuation of a power supply

1994-12-06

1996-06-25

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

326 33, 326105, H03K 19003, H03K 19096

Patent

active

055303803

ABSTRACT:
A decoder circuit includes p-channel MOS transistors P.sub.1 and P.sub.2, n-channel MOS transistors N.sub.1 to N.sub.4 having gates to which data signals D.sub.1 to D.sub.4 are inputted, respectively, an n-channel MOS transistor N.sub.s connected in series to the n-channel MOS transistors N.sub.1 to N.sub.4 and having a gate to which the precharging signal .PHI. is inputted, and an n-channel MOS transistor N.sub.5 connected between P.sub.2 and N.sub.1. In the decoder circuit, the gate of N.sub.5 is connected to the drain of P.sub.2, and a capacity C.sub.H is connected between the gate of N.sub.5 and a power potential. In a holding state, the power potential is held by the aid of the capacity C.sub.H connected to the gate of N.sub.5.

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Pretorious et al. "Charge Redistribution and Noise Margins in Domino CMOS Logic" IEEE Transactions on Circuits and Systems vol. CAS-33, No. 8, Aug. 1986, pp. 786-793.
Wang et al. "Novel Dynamic CMOS Logic Free From Problems of Charge Sharing and Clock Skew" International Journal of Electronics vol. 66, No. 5, May 1989, pp. 679-695.

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