Decoder circuit

Details Decoder circuit Decoder circuit

2005-03-08

2005-03-08

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C326S107000, C326S108000, C326S095000

Reexamination Certificate

active

06864721

ABSTRACT:
A decode circuit for selecting one of a plurality of output lines in dependence on the status of a plurality of input lines, the circuit comprising: a first decode arrangement comprising: a first decode node; first precharging circuitry for charging the first decode node to a charging potential; first discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the first decode node to a discharging potential; and first selection circuitry coupled to a respective one of the output lines and operable in response to a first enable signal to select that output line if the first decode node has not discharged; and a second decode arrangement comprising: a second decode node; second precharging circuitry for charging the second decode node to a charging potential; second discharging circuitry comprising a plurality of switching means each operable in dependence on the status of a respective one of the input lines to couple the second decode node to a discharging potential; and second selection circuitry coupled to a respective one of the output lines and operable in response to a second enable signal to select that output line if the second discharge node has not discharged; wherein the first enable signal is derived from the potential of the second decode node.

REFERENCES:
patent: 4063118 (1977-12-01), Nishimura
patent: 5737270 (1998-04-01), Oppold et al.
patent: 5804989 (1998-09-01), Sato
patent: 6081136 (2000-06-01), Khanna et al.
International Search Report issued in International Appl. No. PCT/GB01/0016, dated Jun. 8, 2001 (3 pages).

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