Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2006-10-03
2006-10-03
Chase, Shelly (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
07117425
ABSTRACT:
A Reed Solomon decoder architecture that uses a modified version of the error-evaluator polynomial form having a significantly reduced area of the dominant PDU unit, without loss in iteration time, in slice circuitry, which rotates terms to share a common multiplier and other circuitry. In addition, a B polynomial is stored, and associated overflow flags are implemented, to allow its storage to be minimized using a dual-multiplier arrangement. The decoder for error correcting codes comprises a syndrome calculation circuit, and a polynomial determining unit comprising slices, and a single multiplier in each of the slices, wherein each of the slices is employed a plurality of times in successive clock cycles. A correction circuit comprises a first multiplier employed when a scratch polynomial has overflowed, and a second multiplier employed when not overflowed.
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Fredrickson Lisa
Song Leilei
Agere Systems Inc.
Chase Shelly
LandOfFree
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