Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2005-09-01
2008-10-07
Baker, Stephen M. (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S780000
Reexamination Certificate
active
07434135
ABSTRACT:
When received data is decoded, a CPU stores a value “1”, which is included in a vector obtained by multiplying the received data by a parity check matrix, as the number of parity errors and also stores hard-decision result information corresponding to the number of parity errors in an output candidate information storage area. If the CPU determines that the received data is uncorrectable after the received data is decoded a given number of times, it reads hard-decision result information corresponding to the smallest number of parity errors, which are included in the number of parity errors stored in the output candidate information storage area and outputs it as a decoding result.
REFERENCES:
patent: 6061823 (2000-05-01), Nara
patent: 6686853 (2004-02-01), Shen et al.
patent: 6718508 (2004-04-01), Lodge et al.
patent: 6751770 (2004-06-01), Morelos-Zaragoza
patent: 6865708 (2005-03-01), Wang
patent: 6888897 (2005-05-01), Nazari et al.
patent: 7055090 (2006-05-01), Kikuchi et al.
patent: 7058873 (2006-06-01), Song et al.
patent: 7133853 (2006-11-01), Richardson et al.
patent: 7137060 (2006-11-01), Yu et al.
patent: 7174495 (2007-02-01), Boutillon et al.
patent: 7178080 (2007-02-01), Hocevar
patent: 7178081 (2007-02-01), Lee et al.
patent: 7219288 (2007-05-01), Dielissen et al.
patent: 7237174 (2007-06-01), Eroz et al.
patent: 7243287 (2007-07-01), Cameron et al.
patent: 7251770 (2007-07-01), Bottomley et al.
patent: 7260766 (2007-08-01), Levy et al.
patent: 7266750 (2007-09-01), Patapoutian et al.
patent: 7296216 (2007-11-01), Shen et al.
patent: 7310768 (2007-12-01), Eidson et al.
patent: 7340003 (2008-03-01), Nazari et al.
patent: 7346117 (2008-03-01), Li
patent: 2003/0203435 (2003-10-01), Ashkenazi et al.
patent: 2004/0123216 (2004-06-01), Nefedov
patent: 2004/0140915 (2004-07-01), Shen et al.
patent: 2004-104686 (2004-04-01), None
European Search Report issued by the European Patent Office dated Mar. 10, 2006, for European Patent Application No. 05107528.1.
Ahmed et al., “Performance Analysis of the Adaptive Parity Check Matrix Based Soft-Decision Decoding Algorithm,” IEEE (2004), pp. 1995-1999.
Reid et al., “Convergence and Errors in Turbo-Decoding,” IEEE Transactions on Communications (Dec. 2001), 49:2045-51.
Fossorier, “Iterative Reliability-Based Decoding of Low-Density Parity Check Codes,” IEEE Journal on Selected Areas in Communications (May 2001), 19:908-917.
Blanksby et al., “A 690-mW 1-Gb/s 1024-b, Rate-1/2 Low-Density Parity-Check Code Decoder”, IEEE Journal of Solid-State Circuits, vol. 37, No. 3, pp. 404-412, (2002).
Baker Stephen M.
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
LandOfFree
Decoder and method for decoding low-density parity-check code does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Decoder and method for decoding low-density parity-check code, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Decoder and method for decoding low-density parity-check code will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4015374