Decoder and decoding method

Details Decoder and decoding method Decoder and decoding method

2000-08-10

2003-12-23

Chung, Phung M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S796000

Reexamination Certificate

active

06668351

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a decoding apparatus and method, and more particularly, to a decoding apparatus and method which is capable of suppressing the decoding deterioration in transfer data when a transfer-data modulation method is changed.
BACKGROUND ART
In Japan, the Radio Regulatory Council submitted a report in which digital broadcasting service by the use of a broadcasting satellite (hereinafter called a BS) will be implemented by a BS4 satellite, which will be launched in the future. Data to be transferred includes main information formed of video signals and audio signals, a transfer method indicating a data encoding rate and a modulation method, a TMCC (transmission multiplexing configuration control) signal in which transport stream (TS) information in data is encoded, and fixed information formed of special-pattern data used for stopping propagation of a transfer-data error.
The main information is encoded and transferred by a QPSK (quadrature phase shift keying) modulation method at an encoding rate R of 1/2, 2/3, 3/4, 5/6, or 7/8, or at a TC8PSK (trelliscoded-coded 8 phase shift keying) method at an encoding rate R of 2/3. The TMCC signal and the fixed information are transferred via a BPSK (binary phase shift keying) signal encoded at an encoding rate of 1/2 (R=1/2). An encoding method and a decoding method used when basic modulation methods (TC8PSK, BPSK, and QPSK) are employed in a time-division manner in the above broadcasting method will be described below by referring to FIG.
5
.
An information generator
1
converts the main information, the TMCC signal, and the fixed information, which are binary, to serial data. A serial-to-parallel converter
2
outputs serial data as it is when the serial data is modulated by the BPSK or QPSK modulation method, and converts serial data to two-bit parallel data and outputs it when the serial data is modulated by the TC
8
PSK modulation method.
An encoder
3
convolutionally encodes input data and outputs it. A mapping circuit
4
assigns input data to a BPSK, QPSK, or TC
8
PSK signal point according to the respective modulation methods, and outputs an I signal and a Q signal to a transmission line
5
.
A decoder
6
receives the I signal and the Q signal; decodes it to one-bit data when the convolutionally encoded signals have been modulated by the BPSK or QPSK modulation method, and decodes it to two-bit data when the convolutionally encoded signals have been modulated by the TC
8
PSK modulation method; and outputs the data. A parallel-to-serial converter
7
outputs an input signal as it is when the input signal has been modulated by the BPSK or QPSK modulation method, and converts the two-bit parallel data to serial data and outputs it when the input signal has been modulated by the TC8PSK modulation method. A TMCC controller
8
controls the information generator
1
to the mapping circuit
4
by the use of the TMCC signal.
The information generator
1
will be further described by referring to FIG.
6
. An information output circuit
21
sends the fixed information (TAB
1
and TAB
2
shown in
FIG. 6
) to an input terminal
11
-
1
and an input terminal
11
-
3
of a switching circuit
22
, respectively; sends the TMCC signal (TMCC shown in
FIG. 6
) to an input terminal
11
-
2
; and sends the main information (main information
0
to main information
47
shown in
FIG. 6
) to an input terminal
12
-
0
to an input terminal
12
-
47
, respectively. The switching circuit
22
switches between the input terminals
11
-
1
to
11
-
3
and the input terminals
12
-
0
to
12
-
47
by a signal switcher
13
in a time-division manner, generates each serial data (TAB
1
, TMCC, TAB
2
, and main information
0
to main information
47
), and outputs it to the serial-to-parallel converter
2
.
FIG. 7
shows a frame structure of the data switched by the signal switcher
13
of the switching circuit
22
. One superframe is formed of eight frames, a frame
0
to a frame
7
. The frame
0
is formed of the fixed information TAB
1
, TMCC, the fixed information TAB
2
, and the main information
0
to the main information
47
. A frame
1
to the frame
7
are formed in the similar way to the frame
0
except that the fixed information TAB
2
in the frame
0
is replaced with fixed information TAB
3
. The fixed information TAB
1
, the fixed information TAB
2
, and the fixed information TAB
3
have special patterns of 0x1B95, 0xA340, and 0x5CBF, respectively.
As the encoder
3
, a trellis encoder which performs convolutional encoding will be described below by referring to FIG.
8
. When a signal input from the serial-to-parallel converter
2
has been modulated by a modulation method other than the TC
8
PSK modulation method, an input bit (one bit) is input. When the input signal has been modulated by the TC
8
PSK modulation method, two bits, an input bit and a parallel bit, are input. In any of the modulation methods, the trellis encoder encodes an input bit at an encoding rate R of 1/2 and outputs an output bit
2
and an output bit
3
. The parallel bit is not encoded and output as it is as an output bit
1
. In other words, the trellis encoder encodes a two-bit input signal (input bit and parallel bit) at an encoding rate R of 2/3 to generate three bits.
The input bit is input to a delay circuit
31
formed of a register, an exclusive-OR circuit
33
, and an exclusive-OR circuit
34
. The delay circuit
31
delays the input input bit by a one-time-unit period, and outputs to a delay circuit
32
and the exclusive-OR circuit
33
. The delay circuit
32
formed of a register delays the input input bit by a one-time-unit period and outputs to the exclusive-OR circuit
33
and the exclusive-OR circuit
34
. The exclusive-OR circuit
33
calculates the exclusive OR of the input bit, the signal input from the delay circuit
31
, and the signal input from the delay circuit
32
, every one-time-unit period, and outputs the result as the output bit
2
. The exclusive-OR circuit
34
calculates the exclusive OR of the input bit and the signal input from the delay circuit
32
, every one-time-unit period, and outputs the result as the output bit
3
.
The mapping circuit
4
maps the signal input from the encoder
3
onto signal points shown in
FIG. 9
according to the signal modulation method. FIG.
9
(A) shows signal-point arrangement for the signals (fixed information TAB
1
, fixed information TAB
2
, and TMCC signal) modulated by the BPSK modulation method. FIG.
9
(B) shows signal-point arrangement for the signals (main information
0
to main information
47
) modulated by the TC
8
PSK modulation method. These signal points indicate encoded transfer data which the mapping circuit
4
outputs. Two signal points (for example, a signal point (100) and a signal point (000)) positioned symmetrically against the center of the circle shown in FIG.
9
(B) form a branch of the encoded transfer data. In a branch, one of the signal points has an MSB (most significant bit) of 1 (for example, the MSB of the signal point (100)) and the other has an MSB of 0 (for example, the MSB of the signal point (000)), and the signal points have the same bits (for example, the lower two bits, 00, of the signal point (100) and the signal point (000)) except the MSBs.
A Detailed structure of the decoder
6
will be described below by referring to
FIG. 10. A
branch-metric (hereinafter called BM) generator
41
calculates the square Euclidean distances of the received signals (I, Q) (corresponding to the I coordinate and the Q coordinate in the signal-point arrangement shown in
FIG. 9
) and the signal points (for example, the signal point (000) and the signal point (111) shown in FIG.
9
(B)) of each branch, respectively, and outputs as four BM signals (BM00, BM01, BM10, and BM11). The BM generator
41
also outputs parallel-bit (hereinafter called PB) information (PB00, PB01, PB10, and PB11) selected correspondingly to each branch.
When a receiving point R (−0.173, 0.984) is received as a received signal modulated by t

Affiliated with

Also associated with

Rating

Decoder and decoding method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Decoder and decoding method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Decoder and decoding method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3179423