Static information storage and retrieval – Read/write circuit – Including signal comparison
Patent
1998-07-30
2000-04-11
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Including signal comparison
365241, G11C 1307
Patent
active
060494905
ABSTRACT:
A decoded signal comparison circuit comprises a plurality of decoders, each decoding address signals input in units of at least two bits, the address signals having bits which are input time-sequentially. It also comprises a first register group including a plurality of first registers respectively provided for outputs from the decoders, each first register temporarily storing an output from the corresponding decoder, and a second register group including a plurality of second registers respectively provided for the first registers of the first register group, each second register temporarily storing an output from the corresponding first register. A plurality of bit signal comparison circuits compare a pair of 1-bit signals input thereto. The pair of 1-bit signals consist of the outputs from the first register of the first register group and the second register of the second register group. Each bit signal comparison circuit is activated by one of the pair of 1-bit signals which is output from one of the first and second registers. The number of the bit signal comparison circuits correspond to the number of pairs of first and second registers. A plurality of wired OR circuits are respectively provided for the decoders, for obtaining a logical OR of signals output from the bit signal comparison circuits. A global comparison circuit detects coincidence
on-coincidence of signals output from the wired OR circuits. When the coincidence signal is obtained a Hit signal is outputted.
REFERENCES:
patent: 5933388 (1999-08-01), Choi
Fears Terrell W.
Kabushiki Kaisha Toshiba
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