Decoded autorefresh mode in a DRAM

Details Decoded autorefresh mode in a DRAM Decoded autorefresh mode in a DRAM

1999-03-30

2000-04-04

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Data refresh

36518901, G11C 700

Patent

active

060469536

ABSTRACT:
Dynamic random access memory chips (DRAMs) in a computer memory system are made to be more available for access by a processor even though an autorefresh cycle may be in progress when the processor attempts to access the memory system. A DECODED AUTOREFRESH mode is defined which allows refresh of certain banks of the DRAM only. The bank addresses from the external DRAM controller select the bank where the AUTOREFRESH has to be performed. The DRAM controller circuitry makes sure that every bank of the DRAM gets a refresh command often enough to retain information.

REFERENCES:
patent: 5642320 (1997-06-01), Jang

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